Granted Patent
Utility
US 6,411,563
· Confirmation No. 2066
Semiconductor integrated circuit device provided with a logic circuit and a memory circuit and being capable of efficient interface between the same
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Code | Description | Pages | ||
|---|---|---|---|---|---|
| 2001-03-22 | TRNA |
Transmittal of New Application | 2 | View | |
| 2001-03-22 | SPEC |
Specification | 28 | View | |
| 2001-03-22 | CLM |
Claims | 4 | View | |
| 2001-03-22 | ABST |
Abstract | 1 | View | |
| 2001-03-22 | DRW |
Drawings-only black and white line drawings | 21 | View | |
| 2001-03-22 | OATH |
Oath or Declaration filed | 6 | View |
Inventors
Takaharu Tsuji
Hyogo, JAPAN
Toshiaki Kawasaki
Osaka, JAPAN
Attorneys & Agents of Record
Classification
USPC
365/233
G11C7/109
G11C7/1024
G11C7/1045
G11C7/1072
G11C7/1078
G11C11/4093
G11C2207/104
Prosecution
- Examiner
- LAM, DAVID
- Art Unit
- 2818
- Docket No.
- 57454-051
- Confirmation No.
- 2066
Foreign Priority
2000-256863(P)
·
2000-08-28
·
JAPAN
Publication
- Pub. No.
- US20020024879A1
- Pub. Date
- 2002-02-28
Patent Term Adjustment
0days
No related applications found.
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2020-07-31
CHANGE OF NAME
Recorded 2020-03-18
CHANGE OF ADDRESS
Recorded 2017-11-29
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2011-03-18
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2001-03-22
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Quick Facts
- Patent No.
- US 6,411,563
- App. No.
- 09/814,108
- Filed
- 2001-03-22
- Granted
- 2002-06-25
- Pub. No.
- US20020024879A1
- Examiner
- LAM, DAVID
- Art Unit
- 2818
- PTA
- 0 days
External Links