Method and apparatus for simultaneous optimization of code targeting multiple machines
View Patent ↗Method and apparatus for simultaneous optimization of the compiler to generate codes that may be compatible and acceptable for two or more different processors without potentially sacrificing the performance on any processors is provided. In particular, the rules of instructions scheduling for the machines of interest of different processors are abstracted. From the abstractions, a hypothetical machine is generated that is the restrictive or constraining set of the actual machines modeled in the abstraction step. After generating the hypothetical machine, the restricted hypothetical machine is targeted rather than the actual machines modeled in the first step. Thereafter, conflicts, if any are resolved by modeling the performance impact and selecting the less damaging choice. In this manner, by creating a hypothetical machine model which incorporates the features of all target machines of interest and which is more restrictive or constrained that the actual machines modeled, it is possible to simultaneously optimize the code targeting multiple machines.
1. A method of simultaneously optimizing code for at least two target machines, comprising:
abstracting a rule of instruction scheduling for each of said at least two target machines;
generating a hypothetical machine model of a hypothetical machine based on said rule of instruction scheduling for each of said at least two target machines, wherein a rule of instruction scheduling for said hypothetical machine is a restrictive set of said rule of instruction scheduling for each of said at least two target machines; and
optimizing code using said hypothetical machine model, said optimized code targeting said hypothetical machine, wherein said hypothetical machine model is capable of operating on each of said at least two target machines.
2. The method of claim 1 further including:
detecting a conflict between said rule of instruction scheduling for each of said at least two target machines; and
resolving said conflict.
3. The method of claim 2 wherein resolving said conflict includes selecting a less damaging option for said detected conflict.
4. The method of claim 2 wherein said detected conflict corresponds to an inherent conflict between said rule of instruction scheduling for each of said at least two target machines.
5. The method of claim 1 further including:
modeling each of said at least two target machines; and
retrieving scheduling information corresponding to each of said at least two target machines.
6. The method of claim 1 wherein said at least two target machines include an UltraSPARC-II configured to operate at a speed of 360 MHz and an UltraSPARC-III configured to operate at a speed of 600 MHz.
7. A method of simultaneously optimizing code for at least two target machines, comprising:
retrieving scheduling information corresponding to each of said at least two target machines;
abstracting a rule of instruction scheduling for each of said at least two target machines;
generating a hypothetical machine model of a hypothetical machine based on said rule of instruction scheduling for each of said at least two target machines, wherein a rule of instruction scheduling for said hypothetical machine is a restrictive set of said rule of instruction scheduling for each of said at least two target machines; and
optimizing code using said hypothetical machine model, said optimized code targeting said hypothetical machine, wherein said hypothetical machine model is capable of operating on each of said at least two target machines.
8. The method of claim 7 further including:
detecting a conflict between said rule of instruction scheduling for each of said at least two target machines; and
resolving said conflict.
9. The method of claim 8 wherein resolving said conflict includes selecting a less damaging option for said detected conflict.
10. The method of claim 8 wherein said detected conflict corresponds to an inherent conflict between said rule of instruction for each of said at least two target machines.
11. A computer apparatus for simultaneously optimizing code for at least two target machines, comprising:
means for abstracting a rule of instruction scheduling for each of said at least two target machines;
means for generating a hypothetical machine model of a hypothetical machine based on said rule of instruction scheduling for each of said at least two target machines, wherein a rule of instruction scheduling for said hypothetical machine is a restrictive set of said rule of instruction scheduling for each of said at least two target machines; and
means for optimizing code using said hypothetical machine model, said optimized code targeting said hypothetical machine, wherein said hypothetical machine model is capable of operating on each of said at least two target machines.
12. The apparatus of claim 11 further including:
means for detecting a conflict between said rule of instruction scheduling for each of said at least two target machines; and
means for resolving said conflict.
13. The apparatus of claim 12 wherein said resolving means includes means for selecting a less damaging option for said detected conflict.
14. The apparatus of claim 12 wherein said detected conflict corresponds to an inherent conflict between said rule of instruction scheduling for each of said at least two target machines.
15. The apparatus of claim 11 further including:
means for modeling each of said at least two target machines; and
means for retrieving scheduling information corresponding to each of said at least two target machines.
16. A computer apparatus for simultaneously optimizing code for a plurality of target machines, comprising:
means for receiving scheduling information corresponding to each of said at least two target machines;
means for abstracting a rule of instruction scheduling for each of said at least two target machines;
means for generating a hypothetical machine model of a hypothetical machine based on said rule of instruction scheduling for each of said at least two target machines, wherein a rule of instruction scheduling for said hypothetical machine is a restrictive set of said rule of instruction scheduling for each of said at least two target machines; and
means for optimizing code using said hypothetical machine model, said optimized code targeting said hypothetical machine, wherein said hypothetical machine model is capable of operating on each of said at least two target machines.
17. A computer apparatus for simultaneously optimizing code for a plurality of target machines, comprising:
means for modeling a plurality of target machines;
means for retrieving scheduling information corresponding to each of said plurality of target machines;
means for abstracting a rule of instruction scheduling for each of said plurality of target machines;
means for generating a hypothetical machine model of a hypothetical machine based on said rule of instruction scheduling for each of said at least two target machines, wherein a rule of instruction scheduling for said hypothetical machine is a restrictive set of said rule of instruction scheduling for each of said at least two target machines; and
means for optimizing code using said hypothetical machine model, said optimized code targeting said hypothetical machine, wherein said hypothetical machine model is capable of operating on each of said at least two target machines;
means for detecting a conflict between said rule of instruction scheduling for each of said plurality of target machines; and
means for resolving said conflict.