Semiconductor device and manufacturing method thereof
View Patent ↗In a CMOS circuit formed on a substrate 101 , a subordinate gate wiring line (a first wiring line) 102 a and main gate wiring line (a second wiring line) 107 a are provided in an n-channel TFT. The LDD regions 113 overlaps the first wiring line 102 a and does not overlap the second wiring line 107 a . Thus, when a gate voltage is applied to the first wiring line, the GOLD structure is formed, while no applying forms the LLD structure. In this way, the GOLD structure and the LLD structure can be used appropriately in accordance with the respective specifications required for the circuits.
1. A semiconductor device including a CMOS circuit formed by an n-channel TFT and a p-channel TFT,
wherein an active layer of the n-channel TFT is sandwiched by a first wiring line and a second wiring line through insulating layers,
wherein the active layer includes a low concentration impurity region that is in contact with a channel formation region;
wherein the low concentration impurity region is formed to overlap the first wiring line and not to overlap the second wiring line; and
wherein the first wiring line is electrically connected with the second wiring line.
2. A semiconductor device including a CMOS circuit formed by an n-channel TFT and a p-channel TFT,
wherein an active layer of the n-channel TFT is sandwiched by a first wiring line and a second wiring line through insulating layers; and
wherein the second wiring line has a portion being a laminate of a first conductive layer and a second conductive layer, and a portion being a laminate of the first conductive layer, the second conductive layer and a third conductive layer.
3. The semiconductor device according to claim 2 , wherein the third conductive layer has a lower resistance value than the first conductive layer and the second conductive layer.
4. The semiconductor device according to claim 2 , wherein at least one of the first wiring line and the second wiring line contains an element selected from the group consisting of tantalum (Ta), titanium (Ti), tungsten (W), molybdenum (Mo), and silicon (Si).
5. The semiconductor device according to claim 2 , wherein the third conductive layer mainly contains one of aluminum (Al) and copper (Cu).
6. A semiconductor device having a pixel matrix circuit that includes a pixel TFT and a storage capacitor formed by an n-channel TFT,
wherein the pixel TFT has a structure that an active layer is sandwiched by a first wiring line and a second wiring line through insulating layers,
wherein the active layer includes a low concentration impurity region that is in contact with a channel formation region;
wherein the low concentration impurity region is formed to overlap the first wiring line and not to overlap the second wiring line; and
wherein the second wiring lines has a portion being a laminate of a first conductive layer and a second conductive layer, and a portion being a laminate of the first conductive layer, the second conductive layer and a third conductive layer.
7. The semiconductor device according to claim 6 , wherein the first wiring line is kept at one of a ground electric potential and a source power supply electric potential.
8. The semiconductor device according to claim 6 , wherein the first wiring line is kept at a floating electric potential.
9. A semiconductor device having a pixel matrix circuit that includes a pixel TFT and a storage capacitor formed by an n-channel TFT,
wherein the pixel TFT has a structure that an active layer is sandwiched by a first wiring line and a second wiring line through insulating layers, and
wherein the second wiring line has a portion being a laminate of a first conductive layer and a second conductive layer, and a portion being a laminate of the first conductive layer, the second conductive layer and a third conductive layer.
10. The semiconductor device according to claim 9 , wherein the third conductive layer has a lower resistance value than the first conductive layer and the second conductive layer.
11. The semiconductor device according to claim 9 , wherein at least one of the first wiring line and the second wiring line contains an element selected from the group consisting of tantalum (Ta), titanium (Ti), tungsten (W), molybdenum (Mo), and silicon (Si).
12. The semiconductor device according to claim 9 , wherein the third conductive layer mainly contains one of aluminum (Al) and copper (Cu).
13. A semiconductor device having a pixel matrix circuit and a driver circuit that are formed on a same substrate,
wherein each of a pixel TFT included in the pixel matrix circuit and an n-channel TFT included in the driver circuit has a structure including an active layer sandwiched by each of a first wiring line and a second wiring line through insulating layers;
wherein each of the active layers includes a low concentration impurity region that is in contact with each of channel formation regions;
wherein each of the low concentration impurity regions is formed to overlap each of the first wiring lines and not to overlap each of the second wiring lines;
wherein at least one of the second wiring lines has a portion being a laminate of a first conductive layer and a second conductive layer, and a portion being a laminate of the first conductive layer, the second conductive layer and a third conductive layer; and
wherein the first wiring line of the pixel TFT is kept at one of a fixed electric potential and a floating electric potential, and the first wiring line of the n-channel TFT included in the driver circuit is kept at the same level of electric potential as the second wiring line of the n-channel TFT included in the driver circuit.
14. The semiconductor device according to claim 13 , wherein at least one of the first wiring line and the second wiring line contains an element selected from the group consisting of tantalum (Ta), titanium (Ti), tungsten (W), molybdenum (Mo), and silicon (Si).
15. The semiconductor device according to any one of claims 1 to 13 and 14 , wherein the semiconductor device is one of an active matrix liquid crystal display and an active matrix EL display.
16. The semiconductor device according to any one of claims 1 to 13 and 14 , wherein the semiconductor device is one selected from the group consisting of a video camera, a digital camera, a projector, a projection TV, a goggle type display, an automobile navigation system, a personal computer, and a portable information terminal.
17. A semiconductor device having a pixel matrix circuit and a driver circuit that are formed on a same substrate,
wherein each of a pixel TFT included in the pixel matrix circuit and an n-channel TFT included in the driver circuit has a structure including an active layer sandwiched by each of a first wiring line and a second wiring line through insulating layers;
wherein each of the active layers includes a low concentration impurity region that is in contact with each of channel formation regions;
wherein each of the low concentration impurity regions is formed to overlap each of the first wiring lines and not to overlap each of the second wiring lines; and
wherein the first wiring line in the driver circuit is electrically connected with the second wiring line in the driver circuit.
18. The semiconductor device according to claim 17 , wherein the semiconductor device is one of an active matrix liquid crystal display and an active matrix EL display.
19. The semiconductor device according to claim 17 , wherein the semiconductor device is one selected from the group consisting of a video camera, a digital camera, a projector, a projection TV, a goggle type display, an automobile navigation system, a personal computer, and a portable information terminal.
20. A semiconductor device having a pixel matrix circuit and a driver circuit that are formed on a same substrate,
wherein each of a pixel TFT included in the pixel matrix circuit and an n-channel TFT included in the driver circuit has a structure including an active layer sandwiched by each of a first wiring line and a second wiring line through insulating layers;
wherein at least one of the second wiring lines has a portion being a laminate of a first conductive layer and a second conductive layer, and a portion being a laminate of the first conductive layer, the second conductive layer and a third conductive layer, and
wherein the first wiring line of the pixel TFT is kept at one of a fixed electric potential and a floating electric potential, and the first wiring line of the n-channel TFT included in the driver circuit is kept at the same level of electric potential as the second wiring line of the n-channel TFT included in the driver circuit.
21. The semiconductor device according to claim 20 , wherein the third conductive layer has a lower resistance value than the first conductive layer and the second conductive layer.
22. The semiconductor device according to claim 20 , wherein at least one of the first wiring line and the second wiring line contains an element selected from the group consisting of tantalum (Ta), titanium (Ti), tungsten (W), molybdenum (Mo), and silicon (Si).
23. The semiconductor device according to claim 20 , wherein the third conductive layer mainly contains one of aluminum (Al) and copper (Cu).
24. The semiconductor device according to claim 20 , wherein the semiconductor device is one of an active matrix liquid crystal display and an active matrix EL display.
25. The semiconductor device according to claim 20 , wherein the semiconductor device is one selected from the group consisting of a video camera, a digital camera, a projector, a projection TV, a goggle type display, an automobile navigation system, a personal computer, and a portable information terminal.
26. The semiconductor device according to claim 1 , wherein at least one of the first wiring line and the second wiring line contains an element selected from the group consisting of tantalum (Ta), titanium (Ti), tungsten (W), molybdenum (Mo), and silicon (Si).
27. The semiconductor device according to claim 2 , wherein the first wiring line is electrically connected with the second wiring line.
28. The semiconductor device according to claim 6 , wherein at least one of the first wiring line and the second wiring line contains an element selected from the group consisting of tantalum (Ta), titanium (Ti), tungsten (W), molybdenum (Mo), and silicon (Si).
29. The semiconductor device according to claim 9 , wherein the first wiring line is kept at one of a ground electric potential and a source power supply electric potential.
30. The semiconductor device according to claim 9 , wherein the first wiring line is kept at a floating electric potential.
31. The semiconductor device according to claim 13 , wherein the first wiring line of the n-channel TFT is electrically connected with the second wiring line of the n-channel TFT.
32. The semiconductor device according to claim 13 , wherein the third conductive layer has a lower resistance value than the first conductive layer and the second conductive layer.
33. The semiconductor device according to claim 13 , wherein the third conductive layer mainly contains one of aluminum (Al) and copper (Cu).
34. The semiconductor device according to claim 17 , wherein at least one of the each of the first wiring line and the second wiring line contains an element selected from the group consisting of tantalum (Ta), titanium (Ti), tungsten (W), molybdenum (Mo), and silicon (Si).
35. The semiconductor device according to claim 20 , wherein the first wiring line of the n-channel TFT is electrically connected with the second wiring line of the n-channel TFT.