IP Library Granted Patent US 6,901,587
Granted Patent B2
US 6,901,587 · App. 09/859,072 · Granted May 31, 2005

Method and system of cache management using spatial separation of outliers

Assignee: Esmertec AG
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Quick Facts
Patent No.
US 6,901,587
App. No.
09/859,072
Granted
May 31, 2005
Kind
B2
Abstract

A method and a system of cache management using spatial separation of outliers. The system includes a dynamic compiler arranged to create compiled fragments of code having dominant code blocks and outliers. Memory coupled to the dynamic compiler is managed by a compiler manager such that dominant code blocks are stored in one portion of the memory and the outliers are stored in another portion of the memory. Storing the dominant path code separate from the outliers increases efficiency of the system.

Claims (62)

1. A computer system comprising:

a dynamic compiler; the dynamic compiler including:

an execution history recorder configured to record the number of times a fragment of code is executed, the execution history recorder having a threshold;

a code-executing interpreter for executing the code coupled to the execution history recorder;

a compiler manager coupled to the execution history recorder;

a compiler coupled to the compiler manager, the compiler arranged to create compiled fragments of code having dominant code blocks and at least one outlier; and

wherein memory is coupled to the dynamic compiler, the memory managed by the compiler manager such that dominant code blocks are stored in one portion of the memory and the at least one outlier is stored in another portion of the memory.

2. A system as claimed in claim 1 , the outlier having instructions to synchronize states.

3. A system as claimed in claim 2 , wherein the outlier is operable to pass control to a block of glue code.

4. A system as claimed in claim 3 , wherein the glue code instructs the code executing interpreter to interpret a non-dominant fragment of code.

5. A system as claimed in claim 4 , wherein the at least one outlier is patched so as to access a compiled version of the non-dominant fragment of code.

6. A system as claimed in claim 1 , the dynamic compiler further including at least two outliers, and wherein dominant fragments of code and the at least two outliers are stored in a code buffer in the memory, the dominant fragments of code filled from one end of the code buffer and the at least two outliers filled from the other end of the code buffer.

7. A system as claimed in claim 1 , the dynamic compiler further including at least two outliers, and wherein dominant fragments of code and the at least two outliers are stored in a code buffer in the memory, the dominant code fragments and at least two outliers filled from the same end of the code buffer.

8. A system as claimed in claim 1 , the dynamic compiler further including a threshold tuner coupled to the execution history recorder, the threshold tuner operable to adjust the threshold of the execution history recorder.

9. A system as claimed in claim 1 , the dynamic compiler further including:

a memory searcher coupled to the code-executing interpreter;

a converter device coupled to the interpreter; and

an execution device coupled to the converter device.

10. A system as claimed in claim 1 , the dynamic compiler further including a queue coupled to the compiler.

11. A system as claimed in claim 1 , the compiler manager having a memory manager that monitors memory available to the compiler.

12. A system as claimed in claim 11 , wherein a deleter is coupled to the memory manager.

13. A system as claimed in claim 1 , wherein the number of times the fragment of code is executed is recorded when the fragment of code is executed by the code-executing interpreter.

14. A system as claimed in claim 1 , wherein the dynamic compiler is a multi-threaded system and the compiler runs on a separate thread so the progress of code execution is not blocked.

15. A system as claimed in claim 1 , wherein the execution history recorder is further configured to record from where a transfer of control into the fragment of code came and to where control is transferred out of the fragment of code.

16. A system as claimed in claim 1 , wherein the execution history recorder is further configured to alert the compiler manager when the fragment of code has been executed the threshold number of times.

17. A system as claimed in claim 16 , wherein the compiler manager administers the queue of frequently executed fragments of code for compilation.

18. A system comprising:

a code-executing interpreter;

a memory searcher coupled to the code-executing interpreter;

a converter device coupled to the code-executing interpreter;

an execution device coupled to the converter device;

an execution history recorder configured to record the number of times a fragment of code is compiled, the execution history recorder coupled to the code-executing interpreter and having a threshold;

a threshold tuner coupled to the execution history recorder, the threshold tuner operable to adjust the threshold of the execution history recorder;

a compiler manager coupled to the execution history recorder;

a compiler coupled to the compiler manager; and

memory coupled to the compiler and managed by the compiler manager such that dominant blocks of code are stored in one portion of the memory and at least one outlier is stored in another portion of the memory.

19. A system as claimed in claim 18 , further comprising a queue coupled to the compiler.

20. A system as claimed in claim 19 , wherein the compiler manager further includes a memory manager that monitors memory available to the compiler.

21. A system as claimed in claim 20 , further comprising a deleter coupled to the memory manager.

22. A system as claimed in claim 18 , wherein the compiler generates compiled fragments of code with only one entry point.

23. A method of compiling computer code, the method comprising:

establishing an execution threshold within a code-executing interpreter;

executing a number of fragments of the computer code;

recording the number of times each of the fragments of code is executed;

queuing one fragment of code for compilation when the number of times the one fragment of code has been executed matches a threshold;

compiling the one fragment of code;

generating outliers related to fragments of code that have not been executed the threshold number of times; and

storing the one compiled fragment of code and the outliers in separate portions of memory.

24. A method as claimed in claim 23 , further comprising adjusting the threshold after it is established.

25. A method as claimed in claim 23 , further comprising monitoring memory available to the compiler.

26. A method as claimed in claim 25 , further comprising deleting code from memory to meet the requirements of the compiler.

27. A method as claimed in claim 23 , further comprising running the compiler on a thread that is separate from a thread of the code-executing interpreter.

28. A method as claimed in claim 23 , further comprising recording a transfer of control into one fragment of code and a transfer out of the one fragment of code.

29. A method as claimed in claim 23 , further comprising searching memory for preexisting compiled versions of fragments of code.

30. A method as claimed in claim 23 , wherein the computer code includes at least one Method, and at least one of the fragments of code includes less than the entire at least one Method.

31. A method as claimed in claim 23 , further comprising performing an exception check.

32. A method claimed as claim 31 , further comprising performing a code optimization.

33. A method as claimed in claim 31 , further comprising interpreting exception code when an exception occurs.

34. A method as claimed in claim 31 , further comprising establishing a link to a bailout device.

35. A method as claimed in claim 31 , further comprising passing control to the code-executing interpreter.

36. A method as claimed in claim 31 , further comprising updating condition states.

37. A method as claimed in claim 36 , further comprising interpreting exception code after updating condition states.

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded Oct 26, 2020
From: JEFFERIES FINANCE LLC
To: RPX CORPORATION
Reel/Frame 054486/0422 →
SECURITY INTEREST Recorded Jun 29, 2018
From: RPX CORPORATION
To: JEFFERIES FINANCE LLC
Reel/Frame 046486/0433 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 10, 2017
From: MYRIAD GROUP, AG
To: RPX CORPORATION
Reel/Frame 044087/0323 →
PATENTEE CHANGE OF ADDRESS Recorded Feb 5, 2016
From: MYRIAD GROUP, AG
To: MYRIAD GROUP, AG
Reel/Frame 037701/0866 →
CHANGE OF NAME Recorded Jul 9, 2009
From: ESMERTEC AG
To: MYRIAD GROUP AG
Reel/Frame 022928/0730 →
CHANGE OF NAME Recorded Jul 7, 2009
From: ESMERTEC AG
To: MYRIAD GROUP AG
Reel/Frame 022917/0525 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 7, 2004
From: INSIGNIA SOLUTIONS, INC.
To: ESMERTEC AG
Reel/Frame 014852/0297 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 9, 2003
From: INSIGNIA SOLUTIONS, PLC
To: ESMERTEC AG
Reel/Frame 014250/0761 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 17, 2001
From: KRAMSKOY, JEREMY PAUL; CHARNELL, WILLIAM THOMAS; DARNELL, STEPHEN; DIAS, BLAISE ABEL ALEC; GUTHRIE, PHILLIPPA JOY; PLUMMER, WAYNE; SEXTON, JEREMY JAMES; WYNN, MICHAEL JOHN; RAUTENBACH, KEITH; THOMAS, STEPHEN PAUL
To: INSIGNIA SOLUTIONS, PLC
Reel/Frame 012093/0246 →
Priority Claims (1)
GB 9825102 · Nov 16, 1998 · national
Continuity (2)
Continuation PCTGB990078800 · Mar 16, 1999
Related Publication 20020108106A1 · Aug 8, 2002