Granted Patent
Utility
US 6,452,827
· Confirmation No. 6761
I/O CIRCUIT OF SEMICONDUCTOR INTEGRATED DEVICE
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⬇ PDF
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Code | Description | Pages | ||
|---|---|---|---|---|---|
| 2001-12-28 | TRNA |
Transmittal of New Application | 2 | View | |
| 2001-12-28 | ABST |
Abstract | 1 | View | |
| 2001-05-31 | TRNA |
Transmittal of New Application | 4 | View | |
| 2001-05-31 | A.PE |
Preliminary Amendment | 7 | View | |
| 2001-05-31 | SPEC |
Specification | 36 | View | |
| 2001-05-31 | CLM |
Claims | 6 | View | |
| 2001-05-31 | ABST |
Abstract | 2 | View | |
| 2001-05-31 | DRW |
Drawings-only black and white line drawings | 4 | View | |
| 2001-05-31 | OATH |
Oath or Declaration filed | 3 | View |
Inventors
Harumi Kawano
Miyazaki-gun, JAPAN
Akihiro Sushihara
Miyazaki-gun, JAPAN
Attorneys & Agents of Record
Classification
USPC
365/51
H03K19/00315
Prosecution
- Examiner
- TRAN, MICHAEL THANH
- Art Unit
- 2818
- Docket No.
- TNK.025D
- Confirmation No.
- 6761
Foreign Priority
10-373243
·
1998-12-28
·
JAPAN
Publication
- Pub. No.
- US20020040984A1
- Pub. Date
- 2002-04-11
Patent Term Adjustment
0days
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Quick Facts
- Patent No.
- US 6,452,827
- App. No.
- 09/867,531
- Filed
- 2001-05-31
- Granted
- 2002-09-17
- Pub. No.
- US20020040984A1
- Examiner
- TRAN, MICHAEL THANH
- Art Unit
- 2818
- PTA
- 0 days
External Links