IP Library › Granted Patent US 6,492,258
Granted Patent Utility
US 6,492,258 · Confirmation No. 8575

METHOD FOR REDUCING STRESS-INDUCED VOIDS FOR 0.25MM AND SMALLER SEMICONDUCTOR CHIP TECHNOLOGY BY ANNEALING INTERCONNECT LINES AND USING LOW BIAS VOLTAGE AND LOW INTERLAYER DIELECTRIC DEPOSITION RATE AND SEMICONDUCTOR CHIP MADE THEREBY

Patented Case View Patent ↗
⬇ PDF
 Code Description Pages PDF
2001-06-14 TRNA Transmittal of New Application 5 View
2001-06-14 A.PE Preliminary Amendment 7 View
2001-06-14 SPEC Specification 9 View
2001-06-14 CLM Claims 3 View
2001-06-14 ABST Abstract 1 View
2001-06-14 DRW Drawings-only black and white line drawings 2 View
2001-06-14 OATH Oath or Declaration filed 4 View
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this application's details
Quick Facts
Patent No.
US 6,492,258
App. No.
09/881,831
Filed
2001-06-14
Granted
2002-12-10
Art Unit
2812
PTA
0 days