IP Library › Assignment 054636/0001
Patent Assignment
Reel/Frame 054636/0001

RELEASE OF SECURITY INTEREST

Recorded: 2020-11-20 Received: 2020-11-20 Pages: 911
Assignor
Assignee
GLOBALFOUNDRIES INC.
PO BOX 309, UGLAND HOUSE, MAPLES CORPORATE SERVICES LIMITED, GRAND CAYMAN, KYX, KY1-1104, CAYMAN ISLANDS
Covered Applications (100)
CONDUCTOR ASSEMBLY STAGING FOR ROBOTIC INSTALLATION
App. No. 17/120,402
→
DUAL LINER SILICIDE
App. No. 15/956,082
→
FIELD EFFECT TRANSISTOR STRUCTURE WITH RECESSED INTERLAYER DIELECTRIC AND METHOD
App. No. 15/956,090
→
LOCAL TRAP-RICH ISOLATION
App. No. 15/951,557
→
CRYSTAL OSCILLATOR AND THE USE THEREOF IN SEMICONDUCTOR FABRICATION
App. No. 15/951,547
→
GRAPHENE CONTACTS ON SOURCE/DRAIN REGIONS OF FINFET DEVICES
App. No. 15/950,291
→
FINFET DEVICE AND METHOD OF MANUFACTURING
App. No. 15/947,479
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MERGED GATE AND SOURCE/DRAIN CONTACTS IN A SEMICONDUCTOR DEVICE
App. No. 15/945,578
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SPACERS FOR TIGHT GATE PITCHES IN FIELD EFFECT TRANSISTORS
App. No. 15/938,412
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SEMICONDUCTOR STRUCTURE INCLUDING LOW-K SPACER MATERIAL
App. No. 15/936,149
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GIMBAL ASSEMBLY TEST SYSTEM AND METHOD
App. No. 15/933,443
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SELF-ALIGNED VIA FORMING TO CONDUCTIVE LINE AND RELATED WIRING STRUCTURE
App. No. 15/933,449
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STACKED NANOWIRE DEVICE WIDTH ADJUSTMENT BY GAS CLUSTER ION BEAM (GCIB)
App. No. 15/925,051
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METHODS FOR FORMING MOSFETS USING SELECTIVE UNDERCUT AT GATE CONDUCTOR AND GATE INSULATOR CORNER
App. No. 15/921,715
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CIRCUIT AND METHOD FOR DETECTING TIME DEPENDENT DIELECTRIC BREAKDOWN (TDDB) SHORTS AND SIGNAL-MARGIN TESTING
App. No. 15/920,677
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LATERAL PiN DIODES AND SCHOTTKY DIODES
App. No. 15/919,744
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FINFET WITH MERGE-FREE FINS
App. No. 15/913,194
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SEMICONDUCTOR STRUCTURE INCLUDING A VARACTOR AND METHOD FOR THE FORMATION THEREOF
App. No. 15/913,344
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TRANSISTOR STRUCTURE WITH VARIED GATE CROSS-SECTIONAL AREA
App. No. 15/911,415
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FULLY DEPLETED SILICON-ON-INSULATOR (FDSOI) TRANSISTOR DEVICE AND SELF-ALIGNED ACTIVE AREA IN FDSOI BULK EXPOSED REGIONS
App. No. 15/912,141
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METHOD TO IMPROVE RELIABILITY OF REPLACEMENT GATE DEVICE
App. No. 15/911,892
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Nanowire-Based Vertical Memory Cell Array having a Metal Layer Interposed between a Common Back Plate and the Nanowires
App. No. 15/906,355
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METHOD AND STRUCTURE FOR PROTECTING GATES DURING EPITAXIAL GROWTH
App. No. 15/904,982
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METHOD, APPARATUS, AND SYSTEM FOR USING A COVER MASK FOR ENABLING METAL LINE JUMPING OVER MOL FEATURES IN A STANDARD CELL
App. No. 15/905,621
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STRUCTURE AND METHOD FOR FULLY DEPLETED SILICON ON INSULATOR STRUCTURE FOR THRESHOLD VOLTAGE MODIFICATION
App. No. 15/901,997
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CONTACT USING MULTILAYER LINER
App. No. 15/901,979
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FIN FIELD EFFECT TRANSISTOR COMPLEMENTARY METAL OXIDE SEMICONDUCTOR WITH DUAL STRAINED CHANNELS WITH SOLID PHASE DOPING
App. No. 15/901,447
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LEDs WITH THREE COLOR RGB PIXELS FOR DISPLAYS
App. No. 15/901,850
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LIGHT EMITTING DIODES (LEDs) WITH INTEGRATED CMOS CIRCUITS
App. No. 15/899,374
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SYMMETRICAL LATERAL BIPOLAR JUNCTION TRANSISTOR AND USE OF SAME IN CHARACTERIZING AND PROTECTING TRANSISTORS
App. No. 15/897,820
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VERTICAL TRANSISTORS AND METHODS OF FORMING SAME
App. No. 15/893,860
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METHOD, APPARATUS, AND SYSTEM HAVING SUPER STEEP RETROGRADE WELL WITH SILICON AND SILICON GERMANIUM FINS
App. No. 15/894,785
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METHOD TO FORM INTERCONNECT STRUCTURE WITH TUNGSTEN FILL
App. No. 15/893,193
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HIGH DOPED III-V SOURCE/DRAIN JUNCTIONS FOR FIELD EFFECT TRANSISTORS
App. No. 15/890,880
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SEMICONDUCTOR DEVICE INCLUDING BURIED CAPACITIVE STRUCTURES AND A METHOD OF FORMING THE SAME
App. No. 15/890,452
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METHOD FOR FIN FORMATION WITH A SELF-ALIGNED DIRECTED SELF-ASSEMBLY PROCESS AND CUT-LAST SCHEME
App. No. 15/890,859
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GATE STRUCTURE WITH DUAL WIDTH ELECTRODE LAYER
App. No. 15/889,321
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DEVICE WITH DIFFUSION BLOCKING LAYER IN SOURCE/DRAIN REGION
App. No. 15/889,367
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ELECTRICAL AND OPTICAL VIA CONNECTIONS ON A SAME CHIP
App. No. 15/886,927
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SOI FINFET FINS WITH RECESSED FINS AND EPITAXY IN SOURCE DRAIN REGION
App. No. 15/884,045
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SEMICONDUCTOR STRUCTURE INCLUDING A PLURALITY OF PAIRS OF NONVOLATILE MEMORY CELLS AND AN EDGE CELL
App. No. 15/883,975
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NOVEL OTPROM FOR POST-PROCESS PROGRAMMING USING SELECTIVE BREAKDOWN
App. No. 15/881,356
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GATE TIE-DOWN ENABLEMENT WITH INNER SPACER
App. No. 15/880,059
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SELF-ALIGNED MIDDLE OF THE LINE (MOL) CONTACTS
App. No. 15/878,486
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INTEGRATED CIURCUIT PRODUCT HAVING A THROUGH-SUBSTRATE-VIA (TSV) AND A METALLIZATION LAYER THAT ARE FORMED AFTER FORMATION OF A SEMICONDUCTOR DEVICE
App. No. 15/877,549
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SELF-ALIGNED FINFET FORMATION
App. No. 15/876,606
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SELF-CONTAINED METROLOGY WAFER CARRIER SYSTEMS
App. No. 15/876,472
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METHOD, APPARATUS, AND SYSTEM HAVING SUPER STEEP RETROGRADE WELL WITH ENGINEERED DOPANT PROFILES
App. No. 15/875,609
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MULTIPLE-LAYER SPACERS FOR FIELD-EFFECT TRANSISTORS
App. No. 15/875,055
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SELF ALIGNED INTERCONNECT STRUCTURES
App. No. 15/875,212
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VERTICAL PILLAR-TYPE FIELD EFFECT TRANSISTOR AND METHOD
App. No. 15/873,935
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PHOTONICS CHIP
App. No. 15/874,210
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WAFER CARRIER PURGE APPARATUSES, AUTOMATED MECHANICAL HANDLING SYSTEMS INCLUDING THE SAME, AND METHODS OF HANDLING A WAFER CARRIER DURING INTEGRATED CIRCUIT FABRICATION
App. No. 15/872,335
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THREE-DIMENSIONAL SCATTEROMETRY FOR MEASURING DIELECTRIC THICKNESS
App. No. 15/870,108
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APPARATUS AND METHOD FOR VECTOR S-PARAMETER MEASUREMENTS
App. No. 15/868,248
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TALL SINGLE-FIN FIN-TYPE FIELD EFFECT TRANSISTOR STRUCTURES AND METHODS
App. No. 15/862,064
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CRACK PREVENT AND STOP FOR THIN GLASS SUBSTRATES
App. No. 15/858,691
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PRODUCING WAFER LEVEL PACKAGING USING LEADFRAME STRIP AND RELATED DEVICE
App. No. 15/858,673
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SPECIAL CONSTRUCT FOR CONTINUOUS NON-UNIFORM ACTIVE REGION FINFET STANDARD CELLS
App. No. 15/857,202
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CONTACT MODULE FOR OPTIMIZING EMITTER AND CONTACT RESISTANCE
App. No. 15/856,525
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MIDDLE OF THE LINE (MOL) CONTACTS WITH TWO-DIMENSIONAL SELF-ALIGNMENT
App. No. 15/851,774
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SEMICONDUCTOR DEVICE RESISTOR STRUCTURE
App. No. 15/848,324
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ELECTRICALLY INSULATED FIN STRUCTURE(S) WITH ALTERNATIVE CHANNEL MATERIALS AND FABRICATION METHODS
App. No. 15/848,371
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STRAIN RETENTION SEMICONDUCTOR MEMBER FOR CHANNEL SIGE LAYER OF PFET
App. No. 15/848,591
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METHODS OF FORMING TRANSISTOR DEVICES WITH DIFFERENT THRESHOLD VOLTAGES AND THE RESULTING DEVICES
App. No. 15/846,365
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DUAL LINER SILICIDE
App. No. 15/847,028
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TRENCH SILICIDE CONTACTS WITH HIGH SELECTIVITY PROCESS
App. No. 15/847,186
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METHOD OF FORMING FIELD EFFECT TRANSISTORS WITH REPLACEMENT METAL GATES AND CONTACTS AND RESULTING STRUCTURE
App. No. 15/844,840
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METHOD AND SYSTEM FOR NON-DESTRUCTIVE METROLOGY OF THIN LAYERS
App. No. 15/845,313
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FORMING DEFECT-FREE RELAXED SiGe FINS
App. No. 15/843,649
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METHODS OF SIMULTANEOUSLY FORMING BOTTOM AND TOP SPACERS ON A VERTICAL TRANSISTOR DEVICE
App. No. 15/840,835
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SPACER DEFINED FIN GROWTH AND DIFFERENTIAL FIN WIDTH
App. No. 15/839,243
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INTEGRATED CIRCUIT STRUCTURE HAVING DEEP TRENCH CAPACITOR AND THROUGH-SILICON VIA AND METHOD OF FORMING SAME
App. No. 15/837,279
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INTEGRATED CIRCUIT PRODUCTS THAT INCLUDE FINFET DEVICES AND A PROTECTION LAYER FORMED ON AN ISOLATION REGION
App. No. 15/833,285
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FLASH MEMORY DEVICE
App. No. 15/831,833
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DIRECTED SURFACE FUNCTIONALIZATION ON SELECTED SURFACE AREAS OF TOPOGRAPHICAL FEATURES WITH NANOMETER RESOLUTION
App. No. 15/828,624
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CONTACTS TO SEMICONDUCTOR SUBSTRATE AND METHODS OF FORMING SAME
App. No. 15/826,939
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Methods of Forming Integrated Circuit Package with Thermally Conductive Pillar
App. No. 15/826,799
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SEMICONDUCTOR STRUCTURE INCLUDING LOW-K SPACER MATERIAL
App. No. 15/825,409
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METHOD TO REDUCE RESISTANCE FOR A COPPER (CU) INTERCONNECT LANDING ON MULTILAYERED METAL CONTACTS, AND SEMICONDUCTOR STRUCTURES FORMED THEREFROM
App. No. 15/820,602
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DEVICES AND METHODS OF FORMING UNMERGED EPITAXY FOR FINFET DEVICE
App. No. 15/821,091
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METHOD TO IMPROVE CRYSTALLINE REGROWTH
App. No. 15/817,362
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TWO-DIMENSIONAL SELF-ALIGNED SUPER VIA INTEGRATION ON SELF-ALIGNED GATE CONTACT
App. No. 15/817,554
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EPITAXIAL AND SILICIDE LAYER FORMATION AT TOP AND BOTTOM SURFACES OF SEMICONDUCTOR FINS
App. No. 15/815,857
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FORMING AIR GAP
App. No. 15/813,399
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FABRICATION OF INTEGRATED CIRCUIT STRUCTURES FOR BIPOLOR TRANSISTORS
App. No. 15/806,532
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FORMING A CONTACT FOR A TALL FIN TRANSISTOR
App. No. 15/801,458
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THROUGH-SILICON VIA WITH IMPROVED SUBSTRATE CONTACT FOR REDUCED THROUGH-SILICON VIA (TSV) CAPACITANCE VARIABILITY
App. No. 15/801,501
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INTERCONNECTION LINES HAVING VARIABLE WIDTHS AND PARTIALLY SELF-ALIGNED CONTINUITY CUTS
App. No. 15/800,551
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METHODS, APPARATUS AND SYSTEM FOR STI RECESS CONTROL FOR HIGHLY SCALED FINFET DEVICES
App. No. 15/801,023
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METHOD FOR COMPENSATING FOR TEMPERATURE EFFECTS IN SEMICONDUCTOR DEVICE STRUCTURES USING A DIODE STRUCTURE AND A TUNABLE RESISTOR
App. No. 15/799,243
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THERMALLY ENHANCED PACKAGE TO REDUCE THERMAL INTERACTION BETWEEN DIES
App. No. 15/799,600
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DRAM STRUCTURE WITH A SINGLE DIFFUSION BREAK
App. No. 15/797,533
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INTEGRATED CIRCUIT STRUCTURE WITHOUT GATE CONTACT AND METHOD OF FORMING SAME
App. No. 15/797,634
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FORMATION OF BOTTOM JUNCTION IN VERTICAL FET DEVICES
App. No. 15/793,545
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INTEGRATED CIRCUIT FABRICATION WITH BORON ETCH-STOP LAYER
App. No. 15/793,419
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TRANSISTOR DEVICE STRUCTURES WITH RETROGRADE WELLS IN CMOS APPLICATIONS
App. No. 15/792,357
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TILED-STRESS-ALLEVIATING PAD STRUCTURE
App. No. 15/791,568
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HYBRID SOURCE AND DRAIN CONTACT FORMATION USING METAL LINER AND METAL INSULATOR SEMICONDUCTOR CONTACTS
App. No. 15/792,206
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TRANSISTOR STRUCTURE HAVING MULTIPLE N-TYPE AND/OR P-TYPE ELONGATED REGIONS INTERSECTING UNDER COMMON GATE
App. No. 15/792,527
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