Self-aligned via forming to conductive line and related wiring structure
A method of forming a via and a wiring structure formed are disclosed. The method may include forming a conductive line in a first dielectric layer; forming a hard mask adjacent to the conductive line after the conductive line forming; forming a second dielectric layer over the hard mask; and forming a via opening to the conductive line in the second dielectric layer. The via opening lands at least partially on the hard mask to self-align the via opening to the conductive line. A via may be formed by filling the via opening with a conductor.
1. A wiring structure for an integrated circuit, the wiring structure comprising:
a conductive line in a first dielectric layer;
a hard mask above the first dielectric layer and horizontally displaced from the conductive line;
a first portion of a conformal cap layer over a portion of the conductive line, and a second portion of the conformal cap layer below the hard mask, wherein the hard mask prevents etching of the second portion of the conformal cap layer;
a second dielectric layer over the hard mask; and
a via to the conductive line, the via positioned in the second dielectric layer, wherein a first portion of the via lands at least partially on a top surface of the conductive line and a top surface of the hard mask and a second portion of the via lands between the hard mask and a side surface of the conductive line to self-align the via to the conductive line,
wherein the hard mask is configured to prevent etching a portion of a material therebelow.
2. The wiring structure of claim 1 , wherein the conformal cap layer is selected from the group consisting of: low temperature oxide and silicon dioxide.
3. The wiring structure of claim 1 , wherein the hard mask has a higher dielectric constant than the conformal cap layer.
4. The wiring structure of claim 1 , wherein the top surface of the hard mask extends beyond a top surface of the first portion of the conformal cap layer.
5. The wiring structure of claim 1 , wherein the hard mask has a higher etch selectivity than the first portion of the conformal cap layer.
6. The wiring structure of claim 1 , wherein the conductive line includes a pair of conductive lines, and wherein the hard mask is positioned between the pair of conductive lines.
7. The wiring structure of claim 1 , wherein the hard mask is selected from the group consisting of: silicon nitride, silicon oxygen carbon nitride, silicon boron carbon nitride and aluminum oxide.
8. A wiring structure for an integrated circuit, the wiring structure comprising:
a pair of conductive lines in a first dielectric layer;
a hard mask horizontally displaced between the pair of conductive lines in the first dielectric layer;
a first portion of a conformal cap layer over a portion of one of the pair of conductive lines, and a second portion of the conformal cap layer below the hard mask, wherein the hard mask prevents etching of the second portion of the conformal cap layer;
a second dielectric layer over the hard mask; and
a via to one of the pair of conductive lines, the via positioned in the second dielectric layer, wherein a first portion of the via lands at least partially on a top surface of the conductive line and a top surface of the hard mask and a second portion of the via lands between the hard mask and a side surface of one of the pair of conductive lines to self-align the via to one of the pair of conductive lines,
wherein the hard mask is configured to prevent etching a portion of a material therebelow.
9. The wiring structure of claim 8 , wherein the conformal cap layer includes one of low temperature oxide or silicon dioxide.
10. The wiring structure of claim 8 , wherein the hard mask has a higher dielectric constant than the conformal cap layer.
11. The wiring structure of claim 8 , wherein the top surface of the hard mask extends beyond a top surface of the first portion of the conformal cap layer.
12. The wiring structure of claim 8 , wherein the hard mask has a higher etch selectivity than the conformal cap layer.
13. The wiring structure of claim 8 , wherein the hard mask includes one of silicon nitride, silicon oxygen carbon nitride, silicon boron carbon nitride, or aluminum oxide.
14. A wiring structure for an integrated circuit, the wiring structure comprising:
a conductive line in a first dielectric layer;
a hard mask above the first dielectric layer and horizontally displaced from the conductive line, wherein the hard mask includes one of silicon nitride, silicon oxygen carbon nitride, silicon boron carbon nitride, or aluminum oxide;
a second dielectric layer over the hard mask;
a conformal cap layer having a first portion over the conductive line, and a second portion below the hard mask, the conformal cap layer including one of low temperature oxide or silicon dioxide, wherein the hard mask prevents etching of the second portion of the conformal cap layer; and
a via to the conductive line, the via positioned in the second dielectric layer, wherein a first portion of the via lands at least partially on a top surface of the conductive line and a top surface of the hard mask and a second portion of the via lands between the hard mask and a side surface of the conductive line to self-align the via to the conductive line,
wherein the hard mask is configured to prevent etching a portion of a material therebelow.
15. The wiring structure of claim 14 , wherein the conductive line includes a pair of conductive lines, and wherein the hard mask is positioned between the pair of conductive lines.
16. The wiring structure of claim 14 , wherein the hard mask has a higher dielectric constant than the conformal cap layer.
17. The wiring structure of claim 14 , wherein the top surface of the hard mask extends beyond a top surface of the first portion of the conformal cap layer.
18. The wiring structure of claim 14 , wherein the hard mask has a higher etch selectivity than the conformal cap layer.