Patent Assignment
Reel/Frame 054633/0001
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded: 2020-11-02
Received: 2020-11-02
Pages: 1245
Assignor
GLOBALFOUNDRIES INC.
Executed: 2020-10-22
Assignee
GLOBALFOUNDRIES U.S. INC.
2600 GREAT AMERICA WAY, SANTA CLARA, CA, 95054, UNITED STATES
Covered Applications
(100)
MIDDLE OF LINE STRUCTURES
App. No. 17/012,266
→
NON-VOLATILE STATIC RANDOM ACCESS MEMORY
App. No. 17/007,512
→
DEVICE COMPRISING AN OPTOFLUIDIC SENSOR WITH INTEGRATED PHOTODIODE
App. No. 17/006,050
→
CONDUCTIVE ATOMIC FORCE MICROSCOPY SYSTEM WITH ENHANCED SENSITIVITY AND METHODS OF USING SUCH A SYSTEM
App. No. 17/005,883
→
WAFER WITH LOCALIZED SEMICONDUCTOR ON INSULATOR REGIONS WITH CAVITY STRUCTURES
App. No. 17/003,179
→
ELECTROSTATIC DISCHARGE DEVICE
App. No. 17/001,009
→
MEMORY CELL HAVING A FREE FERROMAGNETIC MATERIAL LAYER WITH A CURVED, NON-PLANAR SURFACE AND METHODS OF MAKING SUCH MEMORY CELLS
App. No. 16/997,065
→
FIELD EFFECT TRANSISTOR WITH ASYMMETRIC GATE STRUCTURE AND METHOD
App. No. 16/996,010
→
SINGLE DIFFUSION BREAKS INCLUDING STACKED DIELECTRIC LAYERS
App. No. 16/994,915
→
BULK SEMICONDUCTOR STRUCTURE WITH A MULTI-LEVEL POLYCRYSTALLINE SEMICONDUCTOR REGION AND METHOD
App. No. 16/992,165
→
STRUCTURE WITH POLYCRYSTALLINE ISOLATION REGION BELOW POLYCRYSTALLINE FILL SHAPE(S) AND SELECTIVE ACTIVE DEVICE(S), AND RELATED METHOD
App. No. 16/992,445
→
STRUCTURE WITH POLYCRYSTALLINE ACTIVE REGION FILL SHAPE(S), AND RELATED METHOD
App. No. 16/992,440
→
ROW-WISE TRACKING OF REFERENCE GENERATION FOR MEMORY DEVICES
App. No. 16/990,441
→
MULTIMODE WAVEGUIDE BENDS WITH FEATURES TO REDUCE BENDING LOSS
App. No. 16/989,214
→
DEVICES WITH STAGGERED BODY CONTACTS
App. No. 16/987,170
→
EDGE COUPLERS WITH A PARTIALLY-ETCHED INVERSE TAPER
App. No. 16/985,645
→
STRUCTURES AND SRAM BIT CELLS INTEGRATING COMPLEMENTARY FIELD-EFFECT TRANSISTORS
App. No. 16/984,468
→
INTEGRATED CIRCUIT STRUCTURE WITH AVALANCHE JUNCTION TO DOPED SEMICONDUCTOR OVER SEMICONDUCTOR WELL
App. No. 16/983,071
→
FIN-TYPE FIELD EFFECT TRANSISTOR WITH REDUCED FIN BULGE AND METHOD
App. No. 16/942,816
→
SYMMETRIC ARRANGEMENT OF FIELD PLATES IN SEMICONDUCTOR DEVICES
App. No. 16/942,734
→
SEMICONDUCTOR DEVICE COMPRISING METAL-INSULATOR-METAL (MIM) CAPACITOR
App. No. 16/941,423
→
TRANSISTOR WITH EMBEDDED ISOLATION LAYER IN BULK SUBSTRATE
App. No. 16/939,213
→
TRANSISTORS WITH HYBRID SOURCE/DRAIN REGIONS
App. No. 16/937,821
→
FINFET WITH SHORTER FIN HEIGHT IN DRAIN REGION THAN SOURCE REGION AND RELATED METHOD
App. No. 16/936,524
→
PHOTODIODE AND/OR PIN DIODE STRUCTURES
App. No. 16/935,854
→
Non-Volatile Memory Cell Arrays with a Sectioned Active Region and Methods of Manufacturing Thereof
App. No. 16/935,691
→
III-V COMPOUND SEMICONDUCTOR LAYER STACKS WITH ELECTRICAL ISOLATION PROVIDED BY A TRAP-RICH LAYER
App. No. 16/934,669
→
INTEGRATED CIRCUIT STRUCTURE WITH OPTICAL ABSORBER LAYER OVER OPTICAL GRATING COUPLER
App. No. 16/931,771
→
HIGH VOLTAGE EXTENDED DRAIN MOSFET (EDMOS) DEVICES IN A HIGH-K METAL GATE (HKMG)
App. No. 16/930,547
→
TUNABLE GRATING COUPLERS CONTAINING A MATERIAL WITH A VARIABLE REFRACTIVE INDEX
App. No. 16/922,233
→
Fin-based Laterally Diffused Structure having a Gate with Two Adjacent Metal Layers and Method for Manufacturing the Same
App. No. 16/921,068
→
IC STRUCTURE WITH FIN HAVING SUBFIN EXTENTS WITH DIFFERENT LATERAL DIMENSIONS
App. No. 16/919,225
→
WAVEGUIDE ATTENUATOR
App. No. 16/919,867
→
ELECTRICAL FUSE FORMATION DURING A MULTIPLE PATTERNING PROCESS
App. No. 16/918,053
→
SEMICONDUCTOR TRANSISTORS SUITABLE FOR RADIO-FREQUENCY APPLICATIONS
App. No. 16/917,802
→
DIFFERENTIAL CLOCK DUTY CYCLE CORRECTION WITH HYBRID CURRENT INJECTORS AND TAPERED DIGITAL TO ANALOG CONVERTER
App. No. 16/916,309
→
IMAGE SENSOR INCORPORATING AN ARRAY OF OPTICALLY SWITCHABLE MAGNETIC TUNNEL JUNCTIONS
App. No. 16/911,950
→
HETEROJUNCTION BIPOLAR TRANSISTOR WITH MARKER LAYER
App. No. 16/909,376
→
STRUCTURE PROVIDING CHARGE CONTROLLED ELECTRONIC FUSE
App. No. 16/907,600
→
Transistor Device having Sidewall Spacers Contacting Lower Surfaces of an Epitaxial Semiconductor Material
App. No. 16/906,490
→
STRUCTURE WITH DIFFERENT STRESS-INDUCING ISOLATION DIELECTRICS FOR DIFFERENT POLARITY FETS
App. No. 16/903,559
→
SEMICONDUCTOR DEVICES HAVING LATE-FORMED ISOLATION STRUCTURES
App. No. 16/901,417
→
MULTIPLE WAVEGUIDE COUPLING TO ONE OR MORE PHOTODETECTORS
App. No. 16/901,509
→
RETICLE POD CONVERSION PLATE FOR INTERFACING WITH A TOOL
App. No. 16/901,099
→
VIA STRUCTURES FOR USE IN SEMICONDUCTOR DEVICES
App. No. 16/899,543
→
TRANSISTORS WITH SECTIONED EXTENSION REGIONS
App. No. 16/899,086
→
PHOTODIODE AND/OR PIN DIODE STRUCTURES WITH ONE OR MORE VERTICAL SURFACES
App. No. 16/899,028
→
HETEROJUNCTION BIPOLAR TRANSISTOR
App. No. 16/893,855
→
ADJUSTABLE CAPACITORS TO IMPROVE LINEARITY OF LOW NOISE AMPLIFIER
App. No. 16/889,840
→
FIELD-EFFECT TRANSISTORS WITH A POLYCRYSTALLINE BODY IN A SHALLOW TRENCH ISOLATION REGION
App. No. 16/890,063
→
PHOTODIODE AND/OR PIN DIODE STRUCTURES
App. No. 16/887,375
→
MULTIPLE FIN FINFET WITH LOW-RESISTANCE GATE STRUCTURE
App. No. 16/883,492
→
DYNAMIC SINGLE INPUT-DUAL OUTPUT LATCH
App. No. 16/881,053
→
ACTIVE X-RAY ATTACK PREVENTION DEVICE
App. No. 16/881,736
→
OPTICAL NEURO-MIMETIC DEVICES
App. No. 16/880,253
→
SEMICONDUCTOR DEVICES WITH LOW RESISTANCE GATE STRUCTURES
App. No. 16/877,510
→
IC PRODUCT COMPRISING A SINGLE ACTIVE FIN FINFET DEVICE AND AN ELECTRICALLY INACTIVE FIN STRESS REDUCTION STRUCTURE
App. No. 16/876,532
→
SYSTEM AND METHOD FOR PERFORMING THREE-DIMENSIONAL COMPOSITIONAL ANALYSES
App. No. 16/874,712
→
SYSTEM AND METHOD FOR MEASURING ELECTRICAL PROPERTIES OF MATERIALS
App. No. 15/931,792
→
MRAM DEVICE AND METHODS OF MAKING SUCH AN MRAM DEVICE
App. No. 15/930,577
→
WAFER-LEVEL TESTING OF LASERS ATTACHED TO PHOTONICS CHIPS
App. No. 15/930,876
→
CASCADED SENSING CIRCUITS FOR DETECTING AND MONITORING CRACKS IN AN INTEGRATED CIRCUIT
App. No. 16/872,597
→
CIRCUIT STRUCTURE AND METHOD FOR MEMORY STORAGE WITH MEMORY CELL AND MRAM STACK
App. No. 16/871,129
→
NOVEL GATE STRUCTURE FOR AN LDMOS TRANSISTOR DEVICE
App. No. 16/870,356
→
ELECTRO-OPTIC MODULATORS WITH STACKED LAYERS
App. No. 16/868,631
→
PHOTODETECTOR WITH REFLECTOR WITH AIR GAP ADJACENT PHOTODETECTING REGION
App. No. 16/868,773
→
IC STRUCTURE WITH SINGLE ACTIVE REGION HAVING DIFFERENT DOPING PROFILE THAN SET OF ACTIVE REGIONS
App. No. 16/866,663
→
CRACK IDENTIFICATION IN IC CHIP PACKAGE USING ENCAPSULATED LIQUID PENETRANT CONTRAST AGENT
App. No. 16/864,536
→
EDGE COUPLERS WITH STACKED LAYERING
App. No. 16/859,347
→
CASCODE CELL
App. No. 16/857,298
→
FIELD EFFECT TRANSISTOR (FET) STACK AND METHODS TO FORM SAME
App. No. 16/855,236
→
MEMORY DEVICE COMPRISING A TOP VIA ELECTRODE AND METHODS OF MAKING SUCH A MEMORY DEVICE
App. No. 16/855,745
→
ACTIVE ATTACK PREVENTION FOR SECURE INTEGRATED CIRCUITS USING LATCHUP SENSITIVE DIODE CIRCUIT
App. No. 16/855,185
→
FILTER AND AMPLIFICATION CIRCUIT FOR OUTPUTTING ULTRA-WIDE BAND (UWB) RADIO FREQUENCY (RF) SIGNALS WITH A HIGH SPURIOUS-FREE DYNAMIC RANGE, TEST SYSTEM AND METHODS
App. No. 16/853,969
→
SEMICONDUCTOR DEVICE WITH INTERCONNECT TO SOURCE/DRAIN
App. No. 16/854,552
→
Passive devices over polycrystalline semiconductor fins
App. No. 16/853,137
→
POLARIZERS WITH MULTIPLE STACKED LAYERS
App. No. 16/850,350
→
STACKED-WAVEGUIDE POLARIZERS WITH CONDUCTIVE OXIDE STRIPS
App. No. 16/849,355
→
SELF-REFERENCING AND SELF-CALIBRATING INTERFERENCE PATTERN OVERLAY MEASUREMENT
App. No. 16/847,721
→
LOW CLOCK LOAD DYNAMIC DUAL OUTPUT LATCH CIRCUIT
App. No. 16/847,807
→
TOP ELECTRODE FOR A MEMORY DEVICE AND METHODS OF MAKING SUCH A MEMORY DEVICE
App. No. 16/846,497
→
CUP HEIGHT ADJUSTMENT TOOL
App. No. 16/845,629
→
AVALANCHE PHOTODIODE
App. No. 16/844,606
→
THREE PART SOURCE/DRAIN REGION STRUCTURE FOR TRANSISTOR
App. No. 16/843,421
→
DISTRIBUTED BACKSCATTERING GENERATOR AND MONITOR FOR LASER PERFORMANCE CHARACTERIZATION
App. No. 16/842,887
→
METHODS OF FORMING A REPLACEMENT GATE STRUCTURE FOR A TRANSISTOR DEVICE
App. No. 16/843,262
→
PHOTODETECTOR WITH BURIED AIRGAP REFLECTORS
App. No. 16/842,080
→
DEMULTIPLEXER AND RELATED METHOD TO PROCESS MULTIPLEXED OPTICAL INPUTS
App. No. 16/841,963
→
MULTI-LEVEL ISOLATION STRUCTURE
App. No. 16/842,075
→
CRACK DETECTING AND MONITORING SYSTEM FOR AN INTEGRATED CIRCUIT
App. No. 16/838,439
→
OPTICAL COUPLERS WITH SEGMENTED WAVEGUIDES
App. No. 16/837,149
→
MEMORY DEVICE AND METHODS OF MAKING SUCH A MEMORY DEVICE
App. No. 16/836,434
→
MULTI-CHANNEL POWER COMBINER WITH PHASE ADJUSTMENT
App. No. 16/835,303
→
POLARIZERS BASED ON LOOPED WAVEGUIDE CROSSINGS
App. No. 16/836,047
→
MULTIBAND RECEIVERS FOR MILLIMETER WAVE DEVICES
App. No. 16/833,663
→
MICRO-RING MODULATOR
App. No. 16/832,023
→
LOW LEAKAGE GATE STACK FOR A TRANSISTOR DEVICE AND METHODS OF MAKING AN IC PRODUCT THAT INCLUDES SUCH A TRANSISTOR DEVICE
App. No. 16/832,139
→
HETEROJUNCTION BIPOLAR TRANSISTOR
App. No. 16/830,783
→
CORNER STRUCTURES FOR AN OPTICAL FIBER GROOVE
App. No. 16/830,543
→
DISASSEMBLY TOOL FOR ELECTROSTATIC CHUCK
App. No. 16/829,181
→