Structure with different stress-inducing isolation dielectrics for different polarity FETs

1. A structure, comprising:

a first stress-inducing isolation dielectric surrounding a first active region for a p-type field effect transistor (PFET);

a second stress-inducing isolation dielectric surrounding a second active region for an n-type field effect transistor (NFET);

a deep trench opening defined in a space between a first side of each the first and second active regions, the deep trench opening including both the first stress-inducing isolation dielectric and the second stress-inducing isolation dielectric therewithin; and

a gate structure, wherein a lower surface of the gate structure abuts an upper surface of the first stress-inducing isolation dielectric,

wherein the upper surface of the first stress-inducing isolation dielectric is non-coplanar with an upper surface of the second stress-inducing isolation dielectric, and

wherein the first and second stress-inducing isolation dielectrics induce different types of stress.

2. The structure of claim 1 , wherein the first active region of the PFET and the second active region of the NFET are immediately adjacent one another.

3. The structure of claim 1 , further comprising a third isolation dielectric below both the first and second stress-inducing isolation dielectrics in the deep trench opening.

4. The structure of claim 1 , further comprising a shallow trench opening defined in a space to a second, opposing side of each the first and second active regions, each shallow trench opening including one of the first stress-inducing isolation dielectric and the second stress-inducing isolation dielectric.

5. The structure of claim 4 , wherein the first and second active regions are part of a fully-depleted semiconductor-on-insulator (FDSOI) substrate, wherein the deep trench opening extends into a substrate layer of the FDSOI substrate and the shallow trench opening extends into a buried insulator layer of the FDSOI substrate.

6. The structure of claim 1 , wherein each active region has a diffusion length and a smaller diffusion width, and wherein the first stress-inducing isolation dielectric imparts a tensile stress across the diffusion width of the first active region of the PFET and the second stress-inducing isolation dielectric imparts a compressive stress across the diffusion width of the second active region of the NFET.

7. The structure of claim 1 , the first stress-inducing isolation dielectric imparts a tensile stress across a width of the first active region of the PFET and the second stress-inducing isolation dielectric imparts a compressive stress across a width of the second active region of the NFET.

8. The structure of claim 1 , wherein the first stress-inducing isolation dielectric includes one of a semi-atmosphere chemical vapor deposition tetraethyl orthosilicate (SACVD TEOS) based oxide, and a high-density plasma chemical vapor deposition (HDP-CVD) oxide, and the second stress-inducing isolation dielectric includes the other of the SACVD TEOS-based oxide and the HDP-CVD oxide.

9. A structure, comprising:

a trench isolation structure for a p-type field effect transistor (PFET) and an adjacent n-type field effect transistor (NFET), the trench isolation structure comprising:

a trench opening defined in a substrate, a first portion of the trench opening spacing a first active region of the PFET from a second active region of the NFET;

a first stress-inducing isolation dielectric inside the trench opening and surrounding the first active region for the PFET; and

a second stress-inducing isolation dielectric inside the trench opening and surrounding the second active region for the NFET, and

a gate structure positioned over the trench isolation structure, wherein a lower surface of the gate structure abuts an upper surface of the first stress-inducing isolation dielectric,

wherein the upper surface of the first stress-inducing isolation dielectric is non-coplanar with an upper surface of the second stress-inducing isolation dielectric, and

wherein the first and second stress-inducing isolation dielectrics induce different stresses and abut one another in the first portion of the trench opening between the first and second active regions.

10. The structure of claim 9 , further comprising a third isolation dielectric in a lower portion of the first portion of the trench opening under the first and second stress-inducing isolation dielectrics.

11. The structure of claim 10 , wherein the trench opening further includes:

a second portion contiguous with the first portion, the second portion extending to surround the first active region of the PFET and including the first stress-inducing isolation dielectric therein; and

a third portion contiguous with the first portion, the third portion extending to surround the second active region of the NFET and including the second stress-inducing isolation dielectric therein,

wherein the first portion is deeper in the substrate than each of the second and third portions.

12. The structure of claim 9 , wherein each active region has a diffusion length and a smaller diffusion width, and wherein the first stress-inducing isolation dielectric imparts a tensile stress across the diffusion width of the first active region of the PFET and the second stress-inducing isolation dielectric imparts a compressive stress across the diffusion width of the second active region of the NFET.

13. The structure of claim 9 , wherein the first stress-inducing isolation dielectric includes one of a semi-atmosphere chemical vapor deposition tetraethyl orthosilicate (SACVD TEOS) based oxide, and a high-density plasma chemical vapor deposition (HDP-CVD) oxide, and the second stress-inducing isolation dielectric includes the other of the SACVD TEOS-based oxide and the HDP-CVD oxide.

14. The structure of claim 9 , further comprising a third isolation dielectric below both the first and second stress-inducing isolation dielectrics in the first trench opening.

15. A method, comprising:

forming a trench isolation in a substrate surrounding a first active region for a first polarity field effect transistor (FET) and surrounding a second active region for a second, different polarity field effect transistor (FET), the trench isolation including a first stress-inducing isolation dielectric therewithin;

removing a portion of the first stress-inducing isolation dielectric from a portion of the trench isolation surrounding the second active region of the second polarity FET;

forming a second stress-inducing isolation dielectric in the portion of the trench isolation surrounding the second active region for the second polarity FET; and

forming a gate structure positioned over the trench isolation, wherein a lower surface of the gate structure abuts an upper surface of the first stress-inducing isolation dielectric,

wherein the first and second stress-inducing isolation dielectrics induce different types of stress, and

wherein, in a space between the first and second active regions, an upper surface of the first stress-inducing isolation dielectric is non-coplanar with an upper surface of the second stress-inducing isolation dielectric.

16. The method of claim 15 , wherein the first and second stress-inducing isolation dielectrics abut one another in the space between the first and second active regions.

17. The method of claim 15 , wherein forming the trench isolation includes forming a third isolation dielectric in the space between the first and second active regions prior to forming the first and second stress-inducing isolation dielectrics.

18. The method of claim 14 , wherein the first stress-inducing isolation dielectric includes one of a semi-atmosphere chemical vapor deposition tetraethyl orthosilicate (SACVD TEOS) based oxide, and a high-density plasma chemical vapor deposition (HDP-CVD) oxide, and the second stress-inducing isolation dielectric includes the other of the SACVD TEOS-based oxide and the HDP-CVD oxide.