Symmetric arrangement of field plates in semiconductor devices
The present disclosure relates generally to structures in semiconductor devices and methods of forming the same. More particularly, the present disclosure relates to semiconductor devices having field plates that are arranged symmetrically around a gate. The present disclosure provides a semiconductor device including an active region above a substrate, source and drain electrodes in contact with the active region, a gate above the active region and laterally between the source and drain electrodes, a first field plate between the source electrode and the gate, a second field plate between the drain electrode and the gate, in which the gate is spaced apart laterally and substantially equidistant from the first field plate and the second field plate.
1. A semiconductor device comprising:
an active region above a substrate;
source and drain electrodes in contact with the active region;
a gate above the active region and laterally between the source and drain electrodes;
a first field plate between the source electrode and the gate;
a second field plate between the drain electrode and the gate;
wherein the gate is spaced apart laterally and substantially equidistant from the first field plate and the second field plate; and
wherein the first field plate and the second field plate are conductively isolated.
2. The device of claim 1 , wherein the first field plate and the second field plate have upper surfaces that are substantially coplanar with an upper surface of the gate.
3. The device of claim 2 , wherein the first field plate is laterally spaced apart from the source electrode, and the second field plate is laterally spaced apart from the drain electrode.
4. The device of claim 2 , wherein the gate comprises field plate extensions that extend laterally from the gate towards the source and drain electrodes.
5. The device of claim 4 , wherein the field plate extensions are structured symmetrically around the gate.
6. The device of claim 5 , wherein the field plate extensions are spaced apart laterally from the first field plate and the second field plate.
7. The device of claim 6 , wherein the field plate extensions have upper surfaces that are substantially coplanar with the upper surfaces of the first field plate and the second field plate.
8. The device of claim 2 , wherein the active region comprises a barrier layer disposed on a channel layer.
9. The device of claim 8 , further comprising a gate dielectric layer above the channel layer, wherein the gate is disposed on the gate dielectric layer and the gate dielectric layer is spaced apart from an upper surface of the channel layer by a distance between zero to a thickness of the barrier layer.
10. The device of claim 8 , wherein the gate is disposed above the channel layer, and a lower surface of the gate is spaced apart from an upper surface of the channel layer by a distance between zero to a thickness of the barrier layer.
11. The device of claim 8 , further comprising a capping layer upon the barrier layer, wherein the gate is disposed on the capping layer.
12. The device of claim 1 , wherein the first field plate and the second field plate are formed in a first dielectric layer, and further comprising:
a second dielectric layer above the first dielectric layer;
a third field plate and a fourth field plate formed in the second dielectric layer, wherein the third field plate and the fourth field plate are positioned symmetrically around the gate.
13. A method of forming a semiconductor device comprising:
forming an active region above a substrate;
forming a gate above the active region, a first field plate, and a second field plate, the gate being spaced apart laterally and substantially equidistant from the first field plate and the second field plate; and
forming source and drain electrodes to contact the active region, the gate being laterally between the source and drain electrodes, wherein the first field plate is between the source electrode and the gate, and the second field plate is between the drain electrode and the gate, and wherein the first field plate and the second field plate are conductively isolated.
14. A semiconductor device comprising:
an active region above a substrate;
source and drain electrodes in contact with the active region;
a gate above the active region and laterally between the source and drain electrodes;
a first field plate between the source electrode and the gate;
a second field plate between the drain electrode and the gate;
wherein the gate is spaced apart laterally and substantially equidistant from the first field plate and the second field plate; and
wherein the first field plate is electrically coupled to the source electrode and the second field plate is electrically coupled to the drain electrode.
15. The device of claim 14 , wherein the first field plate and the second field plate have upper surfaces that are substantially coplanar with an upper surface of the gate.
16. The device of claim 15 , wherein the first field plate is laterally spaced apart from the source electrode, and the second field plate is laterally spaced apart from the drain electrode.
17. The device of claim 14 , wherein the gate comprises field plate extensions that extend laterally from the gate towards the source and drain electrodes.
18. The device of claim 17 , wherein the field plate extensions are structured symmetrically around the gate.
19. The device of claim 18 , wherein the field plate extensions are spaced apart laterally from the first field plate and the second field plate.
20. The device of claim 19 , wherein the field plate extensions have upper surfaces that are substantially coplanar with the upper surfaces of the first field plate and the second field plate.