Heterojunction bipolar transistor
The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors and methods of manufacture. The structure includes: a first semiconductor layer including a device region; a second semiconductor layer under the first semiconductor layer; a layer of conductive material between the first semiconductor layer and the second semiconductor layer; at least one contact extending to and contacting the layer of conductive material; and a device in the device region above the layer of conductive material.
1. A structure comprising:
a first semiconductor layer including a device region;
a second semiconductor layer under the first semiconductor layer;
a layer of conductive material between the first semiconductor layer and the second semiconductor layer;
at least one contact extending through the first semiconductor layer and contacting the layer of conductive material; and
a device in the device region above the layer of conductive material, the device comprising at least an extrinsic base composed of semiconductor material located on the first semiconductor layer and remote from the at least one contact.
2. The structure of claim 1 , further comprising a deep trench isolation structure surrounding the device region and extending to below the layer of conductive material.
3. The structure of claim 2 , wherein the conductive material is a metal material that extends within a subcollector region and collector region of a heterojunction bipolar transistor.
4. The structure of claim 3 , wherein the metal material is one of Al, Co, Ni, Pt, Ta, W and TiN.
5. The structure of claim 3 , wherein the subcollector region and collector region are within the first semiconductor layer.
6. The structure of claim 1 , wherein the at least one contact is a collector contact of the heterojunction bipolar transistor that extends within the first semiconductor layer and remote from the device.
7. The structure of claim 6 , wherein the collector contact is positioned between the heterojunction bipolar transistor and the deep trench isolation structure.
8. The structure of claim 7 , wherein the collector contact is positioned between a shallow trench isolation structure and the deep trench isolation structure.
9. The structure of claim 1 , wherein the layer of conductive material is bounded by the first semiconductor layer, the second semiconductor layer and a deep trench isolation structure.
10. A structure comprising:
a first semiconductor layer;
a second semiconductor layer under the first semiconductor layer;
a deep trench isolation structure extending through the first semiconductor layer and the second semiconductor layer, and defining a device region;
a transistor within the device region, the transistor comprising at least an extrinsic base over the first semiconductor layer;
a layer of conductive material between the first semiconductor layer and the second semiconductor layer and extending underneath the transistor; and
at least one contact extending through the first semiconductor layer, remote from the extrinsic base and contacting the layer of conductive material.
11. The structure of claim 10 , wherein the transistor is a heterojunction bipolar transistor and the conductive material is a metal material that extends within a subcollector region and collector region of the heterojunction bipolar transistor, the bipolar transistor comprising at least an extrinsic base composed of semiconductor material located on the first semiconductor layer and remote from the at least one contact.
12. The structure of claim 11 , wherein the metal material is one of Al, Co, Ni, W and TiN.
13. The structure of claim 11 , wherein the subcollector region and collector region are within the first semiconductor layer.
14. The structure of claim 11 , wherein the at least one contact is a collector contact of the heterojunction bipolar transistor, positioned between the heterojunction bipolar transistor and the deep trench isolation structure.
15. The structure of claim 14 , wherein the collector contact is positioned between a shallow trench isolation structure and the deep trench isolation structure.
16. The structure of claim 10 , wherein the layer of conductive material is bounded by the first semiconductor layer, the second semiconductor layer and the deep trench isolation structure.
17. The structure of claim 10 , wherein the first semiconductor layer and the second semiconductor layer comprise Si material.
18. The structure of claim 10 , wherein the at least one contact fills an opening within the first semiconductor layer, on a side of the transistor.
19. The structure of claim 10 , wherein:
the conductive material extends between deep trench isolation structures;
the deep trench isolation structures extend below the conductive material and into the second semiconductor layer;
the transistor is between shallow trench isolation structures,
the shallow trench isolation structures extend into the first semiconductor layer;
the shallow trench isolation structures are within a region defined between the deep trench isolation structures;
the transistor comprises a raised extrinsic base region on the first semiconductor layer; and
the at least one contact extends on a side of the raised extrinsic base region, between the shallow trench isolation structures and the deep trench isolation structures.
20. A method comprising:
forming a first semiconductor layer;
forming a second semiconductor layer above the first semiconductor layer;
forming a layer of conductive material on the first semiconductor layer by forming an airgap between the first semiconductor layer and the second semiconductor layer, and filling the air gap with the conductive material;
forming an opening in the second semiconductor layer, extending to the layer of conductive material;
and
forming a device on the second semiconductor layer above the layer of conductive material.