Semiconductor devices with low resistance gate structures

1. A structure comprising:

a substrate;

a first gate structure and a second gate structure in a dielectric layer over the substrate;

the first and second gate structures having a width, wherein the width of the first gate structure is shorter than the width of the second gate structure;

wherein the first gate structure comprises a first gate conductor layer and the second gate structure comprises a second gate conductor layer and a conductive barrier layer;

wherein the first gate conductor layer is made of a different metal from the second gate conductor layer; and

wherein the conductive barrier layer has a higher resistivity than the first gate conductor layer.

2. The structure of claim 1 , wherein the first gate conductor layer is made of cobalt or ruthenium.

3. The structure of claim 2 , wherein the second gate conductor layer is made of tungsten.

4. The structure of claim 1 ,

wherein the conductive barrier layer is arranged next to side surfaces and a bottom surface of the second gate conductor layer.

5. The structure of claim 4 , wherein the conductive barrier layer is made of titanium nitride.

6. The structure of claim 4 further comprising:

a work function metal layer, wherein the work function metal layer is arranged next to side surfaces and a bottom surface of the first gate conductor layer in the first gate structure; and

wherein the work function metal layer is arranged next to side surfaces and a bottom surface of the conductive barrier layer in the second gate structure.

7. The structure of claim 6 further comprising:

a gate dielectric layer, wherein the gate dielectric layer is arranged next to side surfaces and a bottom surface of the work function metal layer.

8. The structure of claim 7 further comprising:

an interfacial dielectric layer, wherein the interfacial dielectric layer is arranged next to a bottom surface of the gate dielectric layer; and

the interfacial dielectric layer forms a bottom surface of the first gate structure and the second gate structure.

9. The structure of claim 1 , wherein the second gate conductor layer occupies more than 50% and up to 90% of volume of the second gate structure.

10. The structure of claim 9 , wherein the first gate conductor layer occupies more than 40% and up to 80% of volume of the first gate structure.

11. The structure of claim 1 , wherein the first gate conductor layer has a higher resistivity than the second gate conductor layer.

12. A structure comprising:

a substrate;

a first gate structure and a second gate structure in a dielectric layer over the substrate;

the first and second gate structures having a width, the width of the second gate structure is at least two times longer than the width of the first gate structure;

wherein the first gate structure comprises a first gate conductor layer and the second gate structure comprises a second gate conductor layer and a conductive barrier layer;

wherein the first gate conductor layer is made of a different metal from the second gate conductor layer; and

wherein the conductive barrier layer has a higher resistivity than the first gate conductor layer.

13. The structure of claim 12 , wherein the substrate comprises a semiconductor fin.

14. The structure of claim 12 further comprising:

spacer structures arranged on side surfaces of the first gate structure and the second gate structure; and

wherein the spacer structures separate the first gate structure and the second gate structure from the dielectric layer.

15. A method to fabricate a structure comprising:

forming a first gate structure and a second gate structure in a dielectric layer over a substrate, the first gate structure having a shorter width than the second gate structure;

wherein the first gate structure comprises a first gate conductor layer and the second gate structure comprises a second gate conductor layer and a conductive barrier layer;

wherein the first gate conductor layer is made of a different metal from the second gate conductor layer; and

wherein the conductive barrier layer has a higher resistivity than the first gate conductor layer.

16. The method of claim 15 further comprising:

providing a first trench and a second trench in a dielectric layer over a substrate, the first trench having a shorter width than the second trench;

forming a first gate conductor layer in the first trench; and

forming a second gate conductor layer in the second trench.

17. The method of claim 16 , wherein the formation of a first gate conductor layer in the first trench further comprises:

depositing a first gate conductor layer in the first trench and the second trench; and

removing the first gate conductor layer from the second trench leaving behind the first gate conductor layer in the first trench.

18. The method of claim 17 , wherein the formation of a second gate conductor layer in the second trench further comprises:

depositing the second gate conductor layer over the first gate conductor layer in the first trench;

depositing the second gate conductor layer in the second trench; and

removing the second gate conductor layer over the first gate conductor layer, leaving behind the second gate conductor layer in the second trench.

19. The method of claim 18 further comprising:

depositing a barrier layer over the first gate conductor layer in the first trench and in the second trench prior to depositing the second gate conductor layer in the first and second trenches; and

removing the barrier layer over the first gate conductor layer in the first trench leaving behind the barrier layer in the second trench.