Structure providing charge controlled electronic fuse
A structure includes a first source/drain region and a second source/drain region in a semiconductor body; and a trench isolation between the first and second source/drain regions in the semiconductor body. A first doping region is about the first source/drain region, a second doping region about the second source/drain region, and the trench isolation is within the second doping region. A third doping region is adjacent to the first doping region and extend partially into the second doping region to create a charge trap section. A gate conductor of a gate structure is over the trench isolation and the first, second, and third doping regions. The charge trap section creates a charge controlled e-fuse operable by applying a stress voltage to the gate conductor.
1. An electronic fuse, comprising:
a first source/drain region and a second source/drain region in a semiconductor body;
a trench isolation between the first and second source/drain regions in the semiconductor body;
a p-well about the first source/drain region;
an n-well about the second source/drain region, creating a source/drain extension adjacent the trench isolation within the n-well;
an n-type doped charge trap section adjacent to the p-well and extending partially into the source/drain extension; and
a gate conductor of a gate structure over the trench isolation and the p-well, the n-well, and the n-type doped charge trap section,
wherein a dopant concentration of the n-type doped charge trap section is at least twice that of the n-well,
wherein the semiconductor body includes a fin over a bulk substrate.
2. The electronic fuse of claim 1 , wherein the n-type doped charge trap section extends from the p-well to an edge of the n-well.
3. The electronic fuse of claim 1 , wherein the n-well is between the trench isolation and the n-type doped charge trap section.
4. The electronic fuse of claim 1 , wherein the n-type doped charge trap section extends from the p-well through the n-well to the trench isolation.
5. The electronic fuse of claim 1 , wherein the n-well is between the second source/drain region and the trench isolation.
6. The electronic fuse of claim 1 , wherein the n-well extends between an upper edge of the n-type doped charge trap section and an upper surface of the semiconductor body.
7. A laterally-diffused metal-oxide semiconductor (LDMOS) device, comprising:
a first source/drain region and a second source/drain region in a semiconductor body;
a trench isolation between the first and second source/drain regions in the semiconductor body;
a p-well about the first source/drain region;
an n-well about the second source/drain region, creating a source/drain extension adjacent the trench isolation within the n-well;
an n-type doped charge trap section adjacent to the p-well and extending partially into the source/drain extension; and
a gate conductor of a gate structure over the trench isolation and the p-well, the n-well, and the n-type doped charge trap section,
wherein a portion of the n-well is between the trench isolation and the n-type doped charge trap section, and
wherein the semiconductor body includes a fin over a bulk substrate.
8. The LDMOS device of claim 7 , wherein the n-well is between the second source/drain region and the trench isolation.
9. The LDMOS device of claim 7 , wherein a dopant concentration of the n-type doped charge trap section is at least twice that of the n-well.
10. An electronic fuse, comprising:
a first source/drain region and a second source/drain region in a semiconductor body;
a trench isolation between the first and second source/drain regions in the semiconductor body;
an n-well about the first source/drain region;
a p-well about the second source/drain region, creating a source/drain extension adjacent the trench isolation within the p-well;
a p-type doped charge trap section adjacent to the n-well and extending partially into the source/drain extension; and
a gate conductor of a gate structure over the trench isolation and the n-well, the p-well, and the p-type doped charge trap section,
wherein a dopant concentration of the p-type doped charge trap section is at least twice that of the p-well.
11. The electronic fuse of claim 10 , wherein the p-type doped charge trap section extends from the n-well to an edge of the p-well.
12. The electronic fuse of claim 10 , wherein the p-well is between the trench isolation and the p-type doped charge trap section.
13. The electronic fuse of claim 10 , wherein the p-type doped charge trap section extends from the n-well through the p-well to the trench isolation.
14. The electronic fuse of claim 10 , wherein the p-well is between the second source/drain region and the trench isolation.
15. The electronic fuse of claim 10 , wherein the p-well extends between an upper edge of the p-type doped charge trap section and an upper surface of the body.
16. The electronic fuse of claim 10 , wherein the semiconductor body includes a fin over a bulk substrate.