Field effect transistor (FET) stack and methods to form same
The disclosure provides a field effect transistor (FET) stack with methods to form the same. The FET stack includes a first transistor over a substrate. The first transistor includes a first active semiconductor material including a first channel region between a first set of source/drain terminals, and a first gate structure over the first channel region. The first gate structure includes a first gate insulator of a first thickness above the first channel region. A second transistor is over the substrate and horizontally separated from the first transistor. A second gate structure of the second transistor may include a second gate insulator of a second thickness above a second channel region, the second thickness being greater than the first thickness. A shared gate node may be coupled to each of the first gate structure and the second gate structure.
1. A field effect transistor (FET) stack, comprising:
a first transistor over a substrate, the first transistor including:
a first active semiconductor material including a first channel region between a first set of source/drain terminals, and
a first gate structure over the first channel region, wherein the first gate structure includes a first gate insulator of a first thickness above the first channel region;
a second transistor over the substrate and horizontally separated from the first transistor, the second transistor including:
a second active semiconductor material including a second channel region between a second set of source/drain terminals, wherein a selected one of the set of second source/drain terminals is coupled to a selected one of the first set of source/drain terminals of the first transistor, and
a second gate structure over the second channel region, wherein the second gate structure includes a second gate insulator of a second thickness above the second channel region, the second thickness being greater than the first thickness;
a shared gate node coupled to each of the first gate structure and the second gate structure,
at least one trench isolation on the substrate between the first active semiconductor material and the second active semiconductor material;
and
a buried insulator layer directly beneath each of the first active semiconductor material and the second active semiconductor material.
2. The FET stack of claim 1 , further comprising a third transistor over the substrate and horizontally between the first transistor and the second transistor, the third transistor including:
a third active semiconductor material including a third channel region between a third set of source/drain terminals, wherein the selected one of the first set of source/drain terminals is coupled to the selected one of the second set of source/drain terminals through the third set of source/drain terminals; and
a third gate structure over the third channel region, wherein the third gate structure includes a third gate insulator of a third thickness above the third channel region, wherein the third thickness is greater than the first thickness and less than the second thickness.
3. The FET stack of claim 2 , wherein a difference between the first thickness and the second thickness is approximately equal to a difference between the second thickness and the third thickness.
4. The FET stack of claim 1 , wherein a gate length of the first gate structure is approximately equal to a gate length of the second gate structure.
5. The FET stack of claim 1 , wherein the first active semiconductor material and the second active semiconductor material are each doped with the same dopant, and wherein the second active semiconductor material has a lower dopant nitrogen concentration than the first active semiconductor material.
6. The FET stack of claim 1 , wherein the second thickness of the second gate insulator is sized to cause a threshold voltage of the second transistor to be greater than a threshold voltage of the first transistor.
7. The FET stack of claim 1 , wherein the FET stack comprises one of a series FET stack or a shunt FET stack within an radio frequency (RF) switching circuit.
8. A field effect transistor (FET) stack, comprising:
a first transistor over a substrate, the first transistor including:
a first active semiconductor material including a first channel region between a first set of source/drain terminals, and
a first gate structure over the first channel region, wherein the first gate structure includes a first gate insulator of a first thickness above the first channel region;
a second transistor over the substrate and horizontally separated from the first transistor, the second transistor including:
a second active semiconductor material including a second channel region between a second set of source/drain terminals, wherein a selected one of the set of second source/drain terminals is coupled to a selected one of the first set of source/drain terminals of the first transistor, and
a second gate structure over the second channel region, wherein the second gate structure includes a second gate insulator of a second thickness above the second channel region, the second thickness being greater than the first thickness; and
a shared gate node coupled to each of the first gate structure and the second gate structure,
wherein the first active semiconductor material and the second active semiconductor material are each doped with the same dopant, and wherein the second active semiconductor material has a lower dopant concentration than the first active semiconductor material.
9. The FET stack of claim 8 , further comprising a third transistor over the substrate and horizontally between the first transistor and the second transistor, the third transistor including:
a third active semiconductor material including a third channel region between a third set of source/drain terminals, wherein the selected one of the first set of source/drain terminals is coupled to the selected one of the second set of source/drain terminals through the third set of source/drain terminals; and
a third gate structure over the third channel region, wherein the third gate structure includes a third gate insulator of a third thickness above the third channel region, wherein the third thickness is greater than the first thickness and less than the second thickness.
10. The FET stack of claim 9 , wherein a difference between the first thickness and the second thickness is approximately equal to a difference between the second thickness and the third thickness.
11. The FET stack of claim 8 , wherein a gate length of the first gate structure is approximately equal to a gate length of the second gate structure.
12. The FET stack of claim 8 , wherein the second thickness of the second gate insulator is sized to cause a threshold voltage of the second transistor to be greater than a threshold voltage of the first transistor.
13. The FET stack of claim 8 , wherein the FET stack comprises one of a series FET stack or a shunt FET stack within an radio frequency (RF) switching circuit.
14. A field effect transistor (FET) stack, comprising:
a first transistor including:
a first active semiconductor material including a first channel region between a first set of source/drain terminals, and
a first gate structure over the first channel region, wherein the first gate structure includes a first gate insulator of a first thickness above the first channel region;
a second transistor including:
a second active semiconductor material including a second channel region between a second set of source/drain terminals, wherein a selected one of the set of second source/drain terminals is coupled to a selected one of the first set of source/drain terminals of the first transistor, and
a second gate structure over the second channel region, wherein the second gate structure includes a second gate insulator of a second thickness above the second channel region, the second thickness being greater than the first thickness;
a gate node coupled to each of the first gate structure and the second gate structure,
a trench isolation between the first active semiconductor material and the second active semiconductor material;
and
a buried insulator layer beneath each of the first active semiconductor material and the second active semiconductor material,
wherein the first active semiconductor material and the second active semiconductor material are each doped with the same dopant, and wherein the second active semiconductor material has a dopant concentration lower than the first active semiconductor material.
15. The FET stack of claim 14 , further comprising a third transistor over the and between the first transistor and the second transistor, the third transistor including:
a third active semiconductor material including a third channel region between a third set of source/drain terminals, wherein the selected one of the first set of source/drain terminals is coupled to the selected one of the second set of source/drain terminals through the third set of source/drain terminals; and
a third gate structure over the third channel region, wherein the third gate structure includes a third gate insulator of a third thickness above the third channel region, wherein the third thickness is greater than the first thickness and less than the second thickness.
16. The FET stack of claim 15 , wherein a difference between the first thickness and the second thickness is approximately equal to a difference between the second thickness and the third thickness.
17. The FET stack of claim 14 , wherein a gate length of the first gate structure is approximately equal to a gate length of the second gate structure.
18. The FET stack of claim 14 , wherein the second thickness of the second gate insulator is sized to cause a threshold voltage of the second transistor to be greater than a threshold voltage of the first transistor.
19. The FET stack of claim 14 , wherein the FET stack comprises one of a series FET stack or a shunt FET stack within an radio frequency (RF) switching circuit.