Cascode cell
The present disclosure relates to semiconductor structures and, more particularly, to unitary Cascode cells with resistance and capacitance optimization, and methods of manufacture. The structure includes a common source FET (CS-FET) in a first portion of a single common semiconductor region, the CS-FET comprising a source region and a drain region, a common gate FET (CG-FET) in a second portion of the single common semiconductor region, the CG-FET comprising a source region and a drain region, and a doped connecting region of the single common semiconductor region, connecting the drain of the CS-FET and the source of the CG-FET.
1. A structure comprising:
a common gate FET (CG-FET) in a first portion of a single common semiconductor region, the CG-FET comprising a source region and drain region;
a common source FET (CS-FET) in a second portion of the single common semiconductor region, the CS-FET comprising the source region and the drain region; and
a doped connecting region of the single common semiconductor region, connecting the drain region of the CS-FET and the source region of the CG-FET.
2. The structure of claim 1 , wherein the doped connecting region is a doped epitaxial region.
3. The structure of claim 1 , wherein the doped connecting region is a diffused region in a substrate.
4. The structure of claim 1 , wherein the single common semiconductor region is an island region in a substrate.
5. The structure of claim 4 , wherein the second portion of the single common semiconductor region is wider than the first portion of the single common semiconductor region.
6. The structure of claim 5 , wherein the first portion has a width W 1 and the second portion has a width W 2 , wherein W 2 is a value which is in a range between being equal to or greater than W 1 and equal to or less than 2×W 1 (two times W 1 ).
7. The structure of claim 6 , wherein the CS-FET has a gate length smaller than a gate length of the CG-FET.
8. The structure of claim 1 , wherein a gate of the CS-FET is configured to receive an RF input signal and the drain region of the CG-FET is configured to provide an RF output signal.
9. The structure of claim 1 , wherein the CS-FET and the CG-FET are selected from a group consisting of at least one of: FinFETs and planer FETs.
10. The structure of claim 9 , wherein the doped connecting region is in a third portion of the single common semiconductor region and includes the drain region of the CS-FET and the source region of the CG-FET.
11. A semiconductor structure comprising:
a common gate FET (CG-FET) in a first portion of a single common semiconductor region; and
a common source FET (CS-FET) in a second portion of the single common semiconductor region;
wherein the single common semiconductor region is a jogged semiconductor region having different widths in different portions of the single common semiconductor region.
12. The structure of claim 11 , wherein the second portion of the single common semiconductor region is wider than the first portion of the single common semiconductor region.
13. The structure of claim 12 , wherein a drain of the CS-FET and a source of the CG-FET are commonly located in a doped connecting region of the single common semiconductor region, connecting the drain of the CS-FET and the source of the CG-FET.
14. The structure of claim 13 , wherein the doped connecting region is a doped epitaxial region.
15. The structure of claim 14 , wherein the single common semiconductor region is an island region in a substrate.
16. The structure of claim 15 , wherein the first portion has a width W 1 and the second portion has a width W 2 , where W 2 includes a value which is in a range of being equal to or greater than W 1 and equal to or less than 2×W 1 (two times W 1 ), and the CS-FET has a gate length smaller than a gate length of the CG-FET.
17. The structure of claim 13 , further comprising a second CS-FET in another portion of the single common semiconductor region, the second CS-FET including the drain connected to the source of a second CG-FET in a different portion of the single common semiconductor region, wherein the different portion is located between the other portion and the doped connecting region, and the CG-FET and the second CG-FET share a common drain region forming an output of a Cascode cell comprised of the CS-FET, the CG-FET and the second CS-FET.
18. A method of forming a Cascode cell comprising:
forming a common gate FET (CG-FET) in a first portion of a single common semiconductor region, the CG-FET comprising a source region and drain region;
forming a common source FET (CS-FET) in a second portion of the single common semiconductor region, the CS-FET comprising the source region and the drain region; and
forming a doped connecting region in the single common semiconductor region, connecting the drain region of the CS-FET and the source region of the CG-FET,
wherein the single common semiconductor region is a jogged semiconductor region having different widths for the first portion and the second portion in the single common semiconductor region.
19. The method of claim 18 , wherein the first portion has a width W 1 and the second portion has a width W 2 , where W 2 is a value in a range of being equal to or greater than W 1 and equal to or less than 2×W 1 (two times W 1 ), and wherein the CS-FET has a gate length smaller than a gate length of the CG-FET.
20. The method of claim 18 , wherein the doped connecting region is a doped epitaxial region.