ROW-WISE TRACKING OF REFERENCE GENERATION FOR MEMORY DEVICES
The present disclosure relates to a structure including a plurality of magnetic random access memory (MRAM) bitcells including a first circuit and a second circuit, the second circuit being connected to a same wordline as the first circuit such that the second circuit is configured as a parallel series connection to generate a reference resistance value for sensing.
1 . A structure comprising a plurality of magnetic random access memory (MRAM) bitcells comprising a first circuit and a second circuit, the second circuit being connected to a same wordline as the first circuit such that the second circuit is configured as a parallel series connection to generate a reference resistance value for sensing,
wherein the first circuit comprises a first bitline connected to a first magnetic tunnel junction (MTJ), the first MTJ is connected to a first transistor, a drain of the first transistor is directly connected to a source of a second transistor, the second transistor is connected to a second MTJ, and the second MTJ is connected to a second bitline, and
a gate of the first transistor and a gate of the second transistor are directly connected to the same wordline.
2 . The structure of claim 1 , wherein the second circuit comprises a reference bit circuit which comprises a plurality of columns for generating the reference resistance value.
3 . The structure of claim 2 , wherein the reference bit circuit comprises a true bitcell which is configured to generate the reference resistance value of (RP+RAP)/2 to enable midpoint sensing, wherein RP comprises a parallel resistance and RAP comprises an anti-parallel resistance.
4 . (canceled)
5 . The structure of claim 1 , wherein each of the first transistor and the second transistor comprise a NFET transistor.
6 . The structure of claim 1 , wherein the reference bit circuit comprises a series combination of a plurality of magnetic tunnel junction (MTJ) bitcells connected in parallel.
7 . The structure of claim 2 , wherein the reference bit circuit comprises a plurality of reference bits which simultaneously are programmed when an array of the MRAM bitcells is being written.
8 . The structure of claim 2 , wherein the reference bit circuit is used to generate the reference resistance value during a read operation of (RP+RAP)/2 to enable midpoint sensing, wherein RP comprises a parallel resistance and RAP comprises an anti-parallel resistance.
9 . The structure of claim 2 , wherein the reference bit circuit generates the reference resistance value from the same wordline as the first circuit, and the first circuit comprises a read/write array circuit.
10 . A circuit, comprising:
a reference bit circuit which comprises a plurality of first columns for generating a reference resistance value; and
a read/write array circuit which comprises a plurality of second columns for performing at least one of a read operation and a write operation,
wherein the reference bit circuit comprises a first bitline connected to a first magnetic tunnel junction (MTJ), the first MTJ is connected to a first transistor, a drain of the first transistor is directly connected to a source of a second transistor, the second transistor is connected to a second MTJ, and the second MTJ is connected to a second bitline, and
a gate of the first transistor and a gate of the second transistor are directly connected to a same wordline.
11 . (canceled)
12 . The circuit of claim 10 , wherein each of the first transistor and the second transistor comprise a NFET transistor.
13 . The circuit of claim 10 , wherein the reference bit circuit comprises a series combination of a plurality of magnetic tunnel junction (MTJ) bitcells connected in parallel.
14 . The circuit of claim 10 , wherein the reference bit circuit comprises a plurality of reference bits which simultaneously are programmed when an array is being written.
15 . The circuit of claim 10 , wherein the reference bit circuit is used to generate the reference resistance value during a read operation of (RP+RAP)/2 to enable midpoint sensing, wherein RP comprises a parallel resistance and RAP comprises an anti-parallel resistance.
16 . The circuit of claim 10 , wherein the reference bit circuit generates the reference resistance value from the same wordline as a wordline of the read/write array circuit.
17 . A method, comprising:
programming a plurality of reference bits in a reference bit circuit which is connected to a read/write array circuit; and
sensing the plurality of reference bits using at least one sense amplifier which is connected to an output of the reference bit circuit,
wherein the reference bit circuit comprises a first bitline connected to a first magnetic tunnel junction (MTJ), the first MTJ is connected to a first transistor, a drain of the first transistor is directly connected to a source of a second transistor, the second transistor is connected to a second MTJ, and the second MTJ is connected to a second bitline, and
a gate of the first transistor and a gate of the second transistor are directly connected to a same wordline.
18 . The method of claim 17 , wherein the plurality of reference bits is programmed in the reference bit circuit using the same wordline as a wordline of the read/write array circuit.
19 . The method of claim 17 , wherein the reference bit circuit comprises a plurality of rows and each of the rows comprise a plurality of magnetic tunnel junctions (MTJs).
20 . The method of claim 19 , wherein the plurality of MTJs comprise sixteen MTJs connected in parallel in each of the rows of the reference bit circuit.
21 . The structure of claim 1 , wherein the second circuit comprises a third bitline connected to a third MTJ, and the third MTJ is connected to a fourth transistor.
22 . The structure of claim 21 , wherein the fourth transistor is connected to a fourth MTJ, and the fourth MTJ is connected to a fourth bitline.