Field-effect transistors with a polycrystalline body in a shallow trench isolation region

1. A structure comprising:

a semiconductor substrate including a first trench;

a shallow trench isolation region comprising a dielectric material in the first trench in the semiconductor substrate, the shallow trench isolation region including a second trench fully surrounded by the dielectric material;

a polycrystalline semiconductor region in the second trench of the shallow trench isolation region, the polycrystalline semiconductor region fully separated from the semiconductor substrate by the dielectric material of the shallow trench isolation region; and

a field-effect transistor including a gate over the polycrystalline semiconductor region and a source/drain region in the polycrystalline semiconductor region.

2. The structure of claim 1 wherein the polycrystalline semiconductor region comprises polysilicon, and the semiconductor substrate comprises single-crystal silicon.

3. The structure of claim 1 wherein the second trench penetrates partially through the dielectric material of the shallow trench isolation region to a lower boundary, and the shallow trench isolation region includes a first portion that is arranged as a margin of the dielectric material between the polycrystalline semiconductor region at the lower boundary of the second trench and the semiconductor substrate adjacent to the lower boundary of the second trench.

4. The structure of claim 3 wherein the shallow trench isolation region includes a plurality of second portions that laterally surround the second trench and the polycrystalline semiconductor region.

5. The structure of claim 4 wherein the semiconductor substrate includes a top surface, and the plurality of second portions of the shallow trench isolation region extend from the top surface of the semiconductor substrate to the first portion of the shallow trench isolation region.

6. The structure of claim 1 wherein the shallow trench isolation region has a top surface, and the polycrystalline semiconductor region has a top surface that is substantially coplanar with the top surface of the shallow trench isolation region.

7. The structure of claim 1 further comprising:

a polycrystalline layer in the semiconductor substrate, the polycrystalline layer arranged beneath the shallow trench isolation region and the polycrystalline semiconductor region.

8. The structure of claim 7 wherein the polycrystalline layer includes a portion that directly contacts the shallow trench isolation region, and the dielectric material of the shallow trench isolation region separates the polycrystalline semiconductor region from the polycrystalline layer.

9. The structure of claim 1 wherein the semiconductor substrate is a bulk substrate.

10. The structure of claim 1 wherein the semiconductor substrate includes a top surface, the first trench has a lower boundary located at a first depth relative to the top surface of the semiconductor substrate, the lower boundary of the second trench is located at a second depth relative to the top surface of the semiconductor substrate, and the second depth is less than the first depth.

11. The structure of claim 1 wherein the dielectric material is silicon dioxide.

12. The structure of claim 1 wherein the shallow trench isolation region includes a margin of the dielectric material between the polycrystalline semiconductor region and the semiconductor substrate.

13. The structure of claim 1 wherein the shallow trench isolation region includes a margin of the dielectric material between the second trench and the semiconductor substrate.

14. The structure of claim 13 wherein the dielectric material is silicon dioxide.