Memory device comprising a top via electrode and methods of making such a memory device
An illustrative device disclosed herein includes at least one layer of insulating material, a conductive contact structure having a conductive line portion and a conductive via portion and a memory cell positioned in a first opening in the at least one layer of insulating material. In this illustrative example, the memory cell includes a bottom electrode, a memory state material positioned above the bottom electrode and an internal sidewall spacer positioned within the first opening and above at least a portion of the memory state material, wherein the internal sidewall spacer defines a spacer opening and wherein the conductive via portion is positioned within the spacer opening and above a portion of the memory state material.
1. A device, comprising:
at least one layer of insulating material;
a conductive contact structure comprising a conductive line portion and a conductive via portion; and
a memory cell positioned in a first opening in the at least one layer of insulating material, the memory cell comprising:
a bottom electrode;
a memory state material positioned above the bottom electrode; and
an internal sidewall spacer positioned within the first opening and above at least a portion of the memory state material, the internal sidewall spacer defining a spacer opening, wherein the conductive via portion is positioned within the spacer opening and above a portion of the memory state material,
wherein the memory state material is positioned on and in physical contact with the bottom electrode, a bottommost surface of the internal sidewall spacer is positioned on and in physical contact with an uppermost surface of the memory state material and the conductive via portion is positioned on and in physical contact with the uppermost surface of the memory state material.
2. The device of claim 1 , wherein a portion of the conductive contact structure is positioned on and in physical contact with an upper surface of the internal sidewall spacer.
3. The device of claim 1 , wherein the at least one layer of insulating material comprises silicon dioxide, the internal sidewall spacer comprises silicon nitride and the memory cell comprises one of an MTJ (magnetic tunnel junction) memory device, an RRAM (resistive random access memory) device, a PRAM (phase-change random access memory) device, an MRAM (magnetic random access memory) device, or a FRAM (ferroelectric random access memory) device.
4. The device of claim 1 , wherein the combination of the internal sidewall spacer and the conductive via portion define a combined volume, wherein the internal sidewall spacer occupies a first portion of the combined volume and the conductive via portion occupies a second portion of the combined volume, wherein the first portion is greater than the second portion.
5. The device of claim 1 , wherein the bottom electrode comprises one of copper, tungsten, ruthenium, aluminum, Ta, Ti, TaN, or TiN, the memory state material comprises one of stoichiometric ZrO 2 , ZnO, HfO 2 , a doped metal oxide, a phase-change chalcoenide, a binary transition metal oxide, a perovskite, a solid-state electrolyte, an organic charge-transfer complex, an organic donor-acceptor system or a two dimension insulating material, and a top electrode of the conductive via portion comprises one of copper, tungsten, ruthenium, aluminum, Ta, Ti, TaN, or TiN.
6. The device of claim 1 , wherein the conductive via portion is conductively coupled to the memory state material.
7. The device of claim 1 , wherein the conductive via portion comprises a single material.
8. The device of claim 1 , further comprising an encapsulation layer positioned around an outer perimeter of the memory cell and between the memory cell and the at least one layer of insulating material.
9. A device, comprising:
at least one layer of insulating material;
a conductive contact structure comprising a conductive line portion and a conductive via portion; and
a memory cell positioned in a first opening in the at least one layer of insulating material, the memory cell comprising:
a bottom electrode;
a memory state material positioned above the bottom electrode; and
an internal sidewall spacer positioned within the first opening and above at least a portion of the memory state material, the internal sidewall spacer defining a spacer opening, wherein the combination of the internal sidewall spacer and the conductive via portion defines a combined volume, wherein the internal sidewall spacer occupies a first portion of the combined volume and the conductive via portion occupies a second portion of the combined volume, wherein the first portion is greater than the second portion,
wherein the memory state material is positioned on and in physical contact with the bottom electrode, a bottommost surface of the internal sidewall spacer is positioned on and in physical contact with an uppermost surface of the memory state material and the conductive via portion is positioned on and in physical contact with the uppermost surface of the memory state material.
10. The device of claim 9 , wherein a portion of the conductive contact structure is positioned on and in physical contact with an upper surface of the internal sidewall spacer.
11. The device of claim 10 , further comprising an encapsulation layer positioned around an outer perimeter of the memory cell and between the memory cell and the at least one layer of insulating material.
12. A device, comprising:
a layer of insulating material;
a conductive contact structure comprising a conductive line portion and a conductive via portion; and
a memory cell positioned in a first opening in the layer of insulating material, the memory cell comprising:
a bottom electrode;
a memory state material positioned above the bottom electrode; and
an internal sidewall spacer positioned within the first opening and above at least a portion of the memory state material, the internal sidewall spacer defining a spacer opening,
wherein the memory state material is positioned on and in physical contact with the bottom electrode, a bottommost surface of the internal sidewall spacer is positioned on and in physical contact with an uppermost surface of the memory state material, and the conductive via portion is positioned within the spacer opening on and in physical contact with the uppermost surface of the memory state material.
13. The device of claim 12 , wherein a portion of the conductive contact structure is positioned on and in physical contact with an upper surface of the internal sidewall spacer.
14. The device of claim 12 , wherein the memory cell comprises one of an MTJ (magnetic tunnel junction) memory device, an RRAM (resistive random access memory) device, a PRAM (phase-change random access memory) device, an MRAM (magnetic random access memory) device, or a FRAM (ferroelectric random access memory) device.
15. The device of claim 12 , wherein the combination of the internal sidewall spacer and the conductive via portion define a combined volume, wherein the internal sidewall spacer occupies a first portion of the combined volume and the conductive via portion occupies a second portion of the combined volume, wherein the first portion is greater than the second portion.