Stacked nanowire device width adjustment by gas cluster ion beam (GCIB)
A method of making a nanowire device includes disposing a first nanowire stack over a substrate, the first nanowire stack including alternating layers of a first and second semiconducting material, the first semiconducting material contacting the substrate and the second semiconducting material being an exposed surface; disposing a second nanowire stack over the substrate, the second nanowire stack including alternating layers of the first and second semiconducting materials, the first semiconducting material contacting the substrate and the second semiconducting material being an exposed surface; forming a first gate spacer along a sidewall of a first gate region on the first nanowire stack and a second gate spacer along a sidewall of a second gate region on the second nanowire stack; oxidizing a portion of the first nanowire stack within the first gate spacer; and removing the first semiconducting material from the first nanowire stack and the second nanowire stack.
1. A method of making a nanowire device, the method comprising:
oxidizing an exposed surface of a nanowire stack to form a dielectric nanowire; and
removing a first semiconducting material layer from the nanowire stack, leaving a second semiconducting material layer remaining in the nanowire stack, the first semiconducting material layer and the second semiconducting material layer comprising different materials;
wherein the dielectric nanowire is arranged on a plurality of the second semiconducting material layers with an open space arranged between the dielectric nanowire and the plurality of the second semiconducting material layers.
2. The method of claim 1 , further comprising forming a gate region on the nanowire stack.
3. The method of claim 2 , further comprising filling the gate region with a high-k metal gate material.
4. The method of claim 2 , further comprising filling the gate region with a sacrificial gate material.
5. The method of claim 4 , wherein the sacrificial gate material is amorphous silicon.
6. The method of claim 4 , wherein the sacrificial gate material is polysilicon.
7. The method of claim 2 , further comprising forming a source region and a drain region on opposing sides of the gate region.
8. The method of claim 7 , wherein the source region and the drain region comprise epitaxial growth.
9. The method of claim 1 , wherein the first semiconducting material layer comprises silicon germanium.
10. The method of claim 4 , wherein the second semiconducting material layer comprises silicon.
11. The method of claim 1 , wherein oxidizing the exposed surface of the nanowire stack comprises a gas cluster ion beam process.
12. The method of claim 1 , wherein oxidizing the exposed surface of the nanowire stack comprises a room temperature oxidation process.
13. The method of claim 1 , wherein oxidizing the exposed surface of the nanowire stack comprises bombarding the nanowire stack with ionized oxygen atoms.
14. The method of claim 1 , wherein oxidizing the exposed surface of the nanowire stack comprises bombarding the nanowire stack with ionized oxygen molecules.
15. The method of claim 1 , wherein the nanowire stack is disposed over an oxide layer that is arranged on the substrate.
16. The method of claim 1 , wherein oxidizing the exposed surface of the nanowire stack comprises a gas cluster ion beam process performed at room temperature.
17. The method of claim 1 , wherein oxidizing the exposed surface of the nanowire stack converts a semiconducting material to a dielectric material.
18. The method of claim 17 , wherein the dielectric material is a dielectric oxide.
19. The method of claim 1 , wherein oxidizing the exposed surface of the nanowire stack converts a semiconducting material to a non-semiconducting material.
20. The method of claim 1 , wherein the dielectric nanowire is electrically inactive.