IP Library Granted Patent US 10,229,855
Granted Patent B2
US 10,229,855 · App. 15/846,365 · Granted Mar 12, 2019

Methods of forming transistor devices with different threshold voltages and the resulting devices

Inventors: Hoon Kim (Clifton Park, NY); Ruilong Xie (Niskayuna, NY); Min Gyu Sung (Latham, NY); Chanro Park (Clifton Park, NY)
Assignee: GLOBALFOUNDRIES Inc.
H01L21/82345H01L21/02181H01L21/28088H01L27/088H01L29/4966H01L29/517H01L29/66545
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Quick Facts
Patent No.
US 10,229,855
App. No.
15/846,365
Granted
Mar 12, 2019
Kind
B2
Abstract

A device includes a first transistor device having a first threshold voltage and including a first gate electrode structure positioned in a first gate cavity. The first gate electrode structure includes a first gate insulation layer, a first barrier layer, a first work function material layer formed above the first barrier layer, a second barrier layer formed above the first work function material layer, and a first conductive material formed above the second barrier layer. A second transistor device has a second threshold voltage different than the first threshold voltage and includes a second gate electrode structure positioned in a second cavity defined in the dielectric layer. The second gate electrode structure includes a second gate insulation layer, a second work function material layer, the second barrier layer formed above the second work function material layer, and a second conductive material formed above the second barrier layer.

Claims (22)

1. A device, comprising:

a first transistor device having a first threshold voltage and including a first gate electrode structure positioned in a first gate cavity, said first gate electrode structure including a first gate insulation layer, a first barrier layer formed above a first portion of said first gate insulation layer, a first work function material layer formed above said first barrier layer, a second barrier layer formed above said first work function material layer and a second portion of said first gate insulation layer, and a first conductive material formed above said second barrier layer; and

a second transistor device having a second threshold voltage different than said first threshold voltage and including a second gate electrode structure positioned in a second gate cavity, said second gate electrode structure including a second gate insulation layer, a second work function material layer formed above a first portion of said second gate insulation layer, said second barrier layer formed above said second work function material layer and a second portion of said second gate insulation layer, and a second conductive material formed above said second barrier layer.

2. The device of claim 1 , wherein said first and second work function material layers are doped with a treatment species comprising one of fluorine, oxygen or nitrogen.

3. The device of claim 1 , wherein said first gate electrode structure has a first work function higher than a second work function of said second gate electrode structure.

4. The device of claim 1 , wherein said first and second gate insulation layers comprise doped high-k gate insulation layers.

5. The device of claim 4 , wherein said doped high-k gate insulation layers comprises hafnium oxide doped with at least one of yttrium or lanthanum.

6. The device of claim 1 , wherein said first and second barrier layers comprise TiN.

7. The device of claim 6 , wherein said first and second work function material layers each comprise a stack of layers.

8. The device of claim 7 , wherein said stack of layers comprise a first layer of TiN, a second layer of TiC positioned above said first layer, and a third layer of TiN positioned above said second layer.

9. The device of claim 1 , wherein an uppermost height of each of said first and second work function material layers is less than an uppermost height of said first and second conductive materials, respectively.

10. The device of claim 1 , wherein said first and second work function material layers comprise a same material.

11. A device, comprising:

a first transistor device having a first threshold voltage and including a first gate electrode structure positioned in a first gate cavity, said first gate electrode structure including a first gate insulation layer, a first barrier layer formed above a first portion of said first gate insulation layer, a first work function material layer formed above said first barrier layer, a second barrier layer formed above said first work function material layer and a second portion of said first gate insulation layer, and a first conductive material formed above said second barrier layer; and

a second transistor device having a second threshold voltage different than said first threshold voltage and including a second gate electrode structure positioned in a second gate cavity, said second gate electrode structure including a second gate insulation layer, a second work function material layer formed above a first portion of said second gate insulation layer, said second barrier layer formed above said second work function material layer and a second portion of said second gate insulation layer, and a second conductive material formed above said second barrier layer, wherein an uppermost height of each of said first and second work function material layers is less than an uppermost height of said first and second conductive materials, respectively, and said first gate electrode structure has a first work function higher than a second work function of said second gate electrode structure.

12. The device of claim 11 , wherein said first and second work function material layers are doped with a treatment species comprising one of fluorine, oxygen or nitrogen.

13. The device of claim 11 , wherein said first and second gate insulation layers comprise doped high-k gate insulation layers.

14. The device of claim 13 , wherein said doped high-k gate insulation layers comprise hafnium oxide doped with at least one of yttrium or lanthanum.

15. The device of claim 11 , wherein said first and second barrier layers comprise TiN.

16. The device of claim 15 , wherein said first and second work function material layers each comprise a stack of layers.

17. The device of claim 16 , wherein said stack of layers comprise a first layer of TiN, a second layer of TiC positioned above said first layer, and a third layer of TiN positioned above said second layer.

18. The device of claim 11 , wherein said first and second work function material layers comprise a same material.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded May 12, 2021
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 056987/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 20, 2020
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES INC.
Reel/Frame 054636/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 2, 2020
From: GLOBALFOUNDRIES INC.
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 054633/0001 →
SECURITY AGREEMENT Recorded Nov 29, 2018
From: GLOBALFOUNDRIES INC.
To: WILMINGTON TRUST, NATIONAL ASSOCIATION
Reel/Frame 049490/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 19, 2017
From: KIM, HOON; SUNG, MIN GYU; XIE, RUILONG; PARK, CHANRO
To: GLOBALFOUNDRIES INC.
Reel/Frame 044906/0489 →
Continuity (2)
Division 14820701 · Aug 7, 2015
Related Publication 20180122702A1 · May 3, 2018