Lateral PiN diodes and schottky diodes
Lateral PiN diodes and Schottky diodes with low parasitic capacitance and variable breakdown voltage structures and methods of manufacture are disclosed. The structure includes a diode with breakdown voltage determined by a dimension between p-and n-terminals formed in an i-region above a substrate.
1. A structure, comprising a diode with breakdown voltage determined by a dimension between p-terminals formed in an i-region above a substrate, wherein the p-terminals are isolated from the substrate by lateral undercut isolation regions, the lateral undercut isolation regions being filled with an insulation material, wherein the diode is a vertical schottky barrier diode with an insulated undercut below a p+ guard ring for reduced parasitic capacitance.
2. The structure of claim 1 , wherein the p-terminals are self aligned.
3. The structure of claim 1 , wherein:
the p-terminals are heavily doped ion implanted regions resistant to a lateral undercut etch selective to the substrate.
4. The structure of claim 1 , wherein the i-region is one of i-Si, i-SiGe, i-SiGeC, and i-SiC grown directly on the underlying substrate.
5. The structure of claim 1 , wherein the substrate comprises silicon.
6. The structure of claim 5 , wherein the i-region directly contacts the substrate.
7. The structure of claim 1 , further comprising an ohmic contact.
8. The structure of claim 7 , wherein the ohmic contact is an n-type ohmic contact.
9. The structure of claim 7 , wherein the ohmic contact extends between the insulation material and the substrate.
10. The structure of claim 7 , wherein the ohmic contact extends between the insulation material and a deep trench isolation structure.
11. A structure, comprising:
a substrate;
an i-region comprising one of i-Si, i-SiGe, i-SiGeC, and i-SiC, formed above the substrate;
a first lateral PiN diode comprising a first p-terminal formed in the i-region at a first distance from a first n-terminal formed in the i-region; and
a second lateral PiN diode comprising a second p-terminal formed in the i-region at a second distance from a second n-terminal formed in the i-region, wherein:
the first distance is greater than the second distance;
the first distance forms a high breakdown voltage region for the first lateral PiN diode; and
the second distance forms a low breakdown voltage region for the second lateral PiN diode,
wherein the first and second p- and n-terminals are isolated from the substrate by lateral undercut isolation regions, each of the lateral undercut isolation regions having an air gap therein, and
the lateral undercut isolation regions comprise a first lateral undercut isolation region extending through a first shallow trench isolation (STI) region and below the first n-terminal, the first lateral undercut isolation region comprising an air gap underneath the first n-terminal.
12. The structure of claim 11 , wherein at least one of:
the first and second p-terminals are heavily doped ion implanted regions resistant to a lateral undercut etch selective to the substrate; and
the first and second n-terminals are heavily doped ion implanted regions resistant to the lateral undercut etch selective to the substrate.
13. The structure of claim 11 , wherein the lateral undercut isolation regions comprise a second lateral undercut isolation region extending through a second shallow trench isolation (STI) region and below the first p-terminal, the second lateral undercut isolation region comprising an air gap underneath the first p-terminal.
14. The structure of claim 13 , wherein the second lateral undercut isolation region extends below the first p-terminal and the second p-terminal.
15. The structure of claim 14 , wherein the air gap in the second lateral undercut isolation region is underneath the first p-terminal and the second p-terminal.
16. A method, comprising:
forming p-terminals and n-terminals in an i-region at different distances to form a high breakdown voltage region and a low breakdown voltage region in an underlying substrate;
etching an opening into the substrate;
selectively etching a lateral undercut in the underlying substrate, under at least one of the p-terminals and n-terminals to remove its direct connection to the underlying substrate; and
at least partially filling the lateral undercut under the at least one of the p-terminals and n-terminals with insulation material to provide an isolation structure under the at least one of the p-terminals and n-terminals.
17. The method of claim 16 , wherein the p-terminals are heavily doped regions which make them resistant to the lateral undercut etch of the underlying substrate.
18. The method of claim 16 , wherein the i-region is one of i-Si, i-SiGe, i-SiGeC, and i-SiC grown directly on the underlying substrate.