Local trap-rich isolation
A trap-rich polysilicon layer is interposed between the active (SOI) layer and the underlying handle portion of a semiconductor substrate to prevent or minimize parasitic surface conduction effects within the active layer and promote device linearity. In various embodiments, the trap-rich layer extends vertically through a portion of an isolation layer and laterally therefrom between the isolation layer and the handle portion of the substrate to underlie a portion of the device active area.
1. A semiconductor device; comprising:
a doped semiconductor layer disposed over an isolation layer of a semiconductor substrate, wherein the isolation layer includes;
spacers on sidewalls of a lateral trench in the isolation layer; and
a trap-rich polysilicon layer embedded between the spacers of the lateral trench within the isolation layer, the trap-rich polysilicon layer extending peripheral to and partially underlying the doped semiconductor layer and spacers.
2. The semiconductor device of claim 1 , wherein the trap-rich polysilicon layer is substantially free of voids.
3. The semiconductor device of claim 1 , wherein a recessed top surface of the trap-rich polysilicon layer is below a top surface of the isolation layer.
4. The semiconductor device of claim 3 , further comprising a dielectric layer disposed on the recessed top surface.
5. The semiconductor device of claim 3 , further comprising a silicide layer disposed on the recessed top surface.
6. The semiconductor device of claim 1 , wherein the isolation layer overlies a handle portion of the semiconductor substrate.
7. The semiconductor device of claim 1 , wherein the doped semiconductor layer comprises an active layer of a switch field effect transistor (FET).
8. The semiconductor device of claim 1 , wherein the spacers comprise silicon nitride, silicon dioxide, silicon oxynitride or a combination thereof.
9. A semiconductor device; comprising:
a doped semiconductor layer disposed over an isolation layer of a semiconductor substrate, wherein the isolation layer includes;
spacers on sidewalls of a lateral trench in the isolation layer;
a trap-rich polysilicon layer embedded between the spacers of the lateral trench within the isolation layer, the trap-rich polysilicon layer extending peripheral to and partially underlying the doped semiconductor layer and spacers;
a gate oxide layer over the doped semiconductor layer and overlying the trap-rich polysilicon layer underlying the doped semiconductor layer; and
a polysilicon gate over the gate oxide layer.