Fully depleted silicon-on-insulator (FDSOI) transistor device and self-aligned active area in FDSOI bulk exposed regions
Methods for eliminating the distance between a BULEX and SOI and the resulting devices are disclosed. Embodiments include providing a silicon layer on a BOX layer on a silicon substrate; forming two active areas in the silicon layer, separated by a space; forming first and second polysilicon gates over one active area, a third polysilicon gate over the space, and fourth and fifth polysilicon gates over the other active area, the second and fourth gates abutting edges of the space; forming spacers at opposite sides of each gate; removing the second, third, and fourth gates and the corresponding spacers; removing the silicon layer and BOX layer in the space, forming a trench and exposing the silicon substrate; forming second spacers on sidewalls of the trench; forming raised source/drain regions on each active area; and forming a p-well contact on the silicon substrate between the second spacers.
1. A device comprising:
a silicon layer over a bulk oxide (BOX) layer over a silicon substrate;
a trench formed in the silicon layer and BOX layer, with the silicon substrate exposed in the trench;
separate spacers formed on sidewalls of the trench, wherein the separate spacers have exposed inner sidewalls;
first and second polysilicon gates, with source/drain regions on the silicon layer between each polysilicon gate and the trench; and
a p-well contact over a top surface of the silicon substrate between the separate spacers.
2. The device according to claim 1 , wherein the source/drain regions are raised source/drain regions.
3. The device according to claim 1 , wherein the source/drain regions extend to the sidewalls of the trench.
4. The device according to claim 1 , wherein the p-well contact has a two contact poly pitch.
5. The device according to claim 4 , wherein the source/drain regions extend one CPP between the trench and each of the first and second polysilicon gates.
6. The device according to claim 1 , wherein the p-well contact has a one CPP.
7. The device of claim 6 , wherein the first and second polysilicon gates have a three CPP.
8. The device of claim 6 , further comprising:
a third polysilicon gate on the silicon layer, adjacent the second polysilicon gate, remote from the trench, the second and third polysilicon gates having a single CPP.
9. A device comprising:
first and second polysilicon gates formed over a silicon-on insulator (SOI) substrate;
first separate spacers formed at opposite sides of the first and second polysilicon gates, wherein the first separate spacers have exposed inner sidewalls;
a trench formed between the first and second polysilicon gates, with a p-well contact formed at the bottom of the trench, and over a top surface of the SOI substrate, wherein second spacers are formed on opposite sides of the trench; and
raised source/drain (S/D) regions formed on the first and second active areas.
10. The device according to claim 9 , wherein the raised S/D regions are epitaxially grown.
11. The device according to claim 10 , wherein the raised S/D regions extend to the sidewalls of the trench.
12. The device according to claim 9 , wherein the p-well contact has a two contact poly pitch.
13. The device according to claim 12 , wherein the raised S/D regions extend one CPP between the trench and each of the first and second polysilicon gates.
14. The device according to claim 9 , wherein the p-well contact has a one CPP.
15. The device of claim 14 , wherein the first and second polysilicon gates have a three CPP.
16. The device of claim 14 , further comprising:
a third polysilicon gate on the silicon layer, adjacent the second polysilicon gate, remote from the trench.
17. The device according to claim 16 , wherein the second and third polysilicon gates have a single CPP.
18. A device comprising:
first and second polysilicon gates formed over a silicon-on insulator (SOI) substrate;
first separate spacers formed at opposite sides of the first and second polysilicon gates the first separate spacers having exposed inner sidewalls;
a trench formed between the first and second polysilicon gates, with a p-well contact formed at the bottom of the trench, and over a top surface of the SOI substrate, wherein second spacers are formed on opposite sides of the trench;
raised source/drain (S/D) regions formed on the first and second active areas; and
a third polysilicon gate over the SOT, adjacent the second polysilicon gate, remote from the trench, and having third spacers formed at opposite sides.
19. The device according to claim 18 , wherein the raised S/D regions extend to the sidewalls of the trench.
20. The device according to claim 18 , wherein the p-well contact has a two contact poly pitch.