Transistor structure with varied gate cross-sectional area
Aspects of the present disclosure include finFET structures with varied cross-sectional areas and methods of forming the same. Methods according to the present disclosure can include, e.g., forming a structure including: a semiconductor fin positioned on a substrate, wherein the semiconductor fin includes: a gate area, and a terminal area laterally distal to the gate area, a sacrificial gate positioned on the gate area of the semiconductor fin, and an insulator positioned on the terminal area of the semiconductor fin; removing the sacrificial gate to expose the gate area of the semiconductor fin; increasing or reducing a cross-sectional area of the gate area of the semiconductor fin; and forming a transistor gate on the gate area of the semiconductor fin.
1. A transistor structure comprising:
a semiconductor fin positioned on a substrate, wherein the semiconductor fin includes:
a first gate area having a first cross-sectional area, and
a terminal area laterally distal to the first gate area and having a second cross-sectional area, wherein the first cross-sectional area is different from the second cross-sectional area;
an epitaxial semiconductor region formed on the first gate area of the semiconductor fin and having a larger height and width than the terminal area of the semiconductor fin, such that the epitaxial semiconductor region contacts an upper surface and sidewalls of the first gate area of the semiconductor fin to enclose the first cross-sectional area;
a transistor gate positioned on the first gate area of the semiconductor fin; and
a contact positioned on the terminal area of the semiconductor fin without contacting the first gate area of the semiconductor fin and directly contacting at least a pair of sidewalls of the epitaxial semiconductor region.
2. The transistor structure of claim 1 , wherein the first cross-sectional area is less than the second cross-sectional area.
3. The transistor structure of claim 1 , wherein the first cross-sectional area is greater than the second cross-sectional area.
4. The transistor structure of claim 1 , further comprising a doped semiconductor region formed on the terminal area of the semiconductor fin, such that an interface between the doped semiconductor region and the terminal area of the semiconductor fin substantially encloses the second cross-sectional area.
5. The transistor structure of claim 1 , wherein the semiconductor fin further includes a second gate area laterally distal to the terminal area and having a third cross-sectional area, wherein the third cross-sectional area is different from the first cross-sectional area and the second cross-sectional area.
6. The transistor structure of claim 1 , wherein a width of the gate area is substantially equal along an entire height of the fin.
7. The transistor structure of claim 1 , wherein a width of the terminal area is substantially equal along an entire height of the fin.
8. The transistor structure of claim 1 , wherein a bottommost surface of the semiconductor fin contacts the substrate.
9. The transistor structure of claim 1 , wherein a height and a width of the gate area is different from a height and a width of the terminal area.
10. A transistor structure comprising:
at least two semiconductor fins laterally separated from one another on a substrate, wherein each of the at least two semiconductor fins includes:
a gate area having a first cross-sectional area, and
a terminal area laterally distal to the gate area and having a second cross-sectional area, wherein the first cross-sectional area is different from the second cross-sectional area;
an epitaxial semiconductor region formed the gate area of at least one semiconductor fin and having a larger height and width than the terminal area of the semiconductor fin, such that the epitaxial semiconductor region contacts an upper surface and sidewalls of the gate area of the semiconductor fin to enclose the first cross-sectional area;
a transistor gate positioned on the gate area of a selected one of the at least two semiconductor fins; and
a contact positioned on the terminal area of the selected one of the at least two semiconductor fins without contacting the gate area thereof, and directly contacting at least a pair of sidewalls of the terminal area region.
11. The transistor structure of claim 10 , wherein the first cross-sectional area is less than the second cross-sectional area.
12. The transistor structure of claim 10 , wherein the first cross-sectional area is greater than the second cross-sectional area.
13. The transistor structure of claim 10 , wherein the first cross-sectional area of the gate area of a first semiconductor fin of the at least two semiconductor fins is substantially equal to the first cross-sectional area of the gate area of a second semiconductor fin of the at least two semiconductor fins.
14. The transistor structure of claim 10 , wherein a width of the gate area is substantially equal along an entire height of the fin.
15. The transistor structure of claim 10 , wherein a height and a width of the gate area is different from a height and a width of the terminal area.
16. A transistor structure comprising:
a semiconductor fin positioned on a substrate, wherein the semiconductor fin includes:
a gate area having a first cross-sectional area, and
a terminal area laterally distal to the gate area and having a second cross-sectional area, wherein the first cross-sectional area is different from the second cross-sectional area;
a transistor gate positioned on the gate area of the semiconductor fin;
an epitaxial semiconductor region formed on the gate area of the semiconductor fin and having a larger height and width than the respective terminal area of the semiconductor fin, such that the epitaxial semiconductor region contacts an upper surface and sidewalls of each gate area of the semiconductor fin to enclose the first cross-sectional area;
a contact positioned on the epitaxial semiconductor region without contacting the gate area of the semiconductor fin and directly contacting at least a pair of sidewalls of the epitaxial semiconductor region; and
a doped semiconductor region formed on the terminal area of the semiconductor fin, wherein the doped semiconductor region encloses the terminal area therein.
17. The transistor structure of claim 16 , wherein the first cross-sectional area is less than the second cross-sectional area.
18. The transistor structure of claim 16 , wherein the first cross-sectional area is greater than the second cross-sectional area.
19. The transistor structure of claim 16 , wherein a width of the gate area is substantially equal along an entire height of the fin.
20. The transistor structure of claim 16 , wherein a height and a width of the gate area is different from a height and a width of the terminal area.