Transistor structure with varied gate cross-sectional area
Aspects of the present disclosure include finFET structures with varied cross-sectional areas and methods of forming the same. Methods according to the present disclosure can include, e.g., forming a structure including: a semiconductor fin positioned on a substrate, wherein the semiconductor fin includes: a gate area, and a terminal area laterally distal to the gate area, a sacrificial gate positioned on the gate area of the semiconductor fin, and an insulator positioned on the terminal area of the semiconductor fin; removing the sacrificial gate to expose the gate area of the semiconductor fin; increasing or reducing a cross-sectional area of the gate area of the semiconductor fin; and forming a transistor gate on the gate area of the semiconductor fin.
1. A method comprising:
forming a structure including:
a semiconductor fin positioned on a substrate, wherein the semiconductor fin includes:
a gate area, and a terminal area laterally distal to the gate area,
a doped semiconductor region positioned on the semiconductor fin,
a sacrificial gate positioned on the doped semiconductor region above the gate area of the semiconductor fin, and
an insulator positioned on the doped semiconductor region above the terminal area of the semiconductor fin;
removing the sacrificial gate and the doped semiconductor region on the gate area of the semiconductor fin to expose the gate area of the semiconductor fin;
changing a cross-sectional area of the gate area of the semiconductor fin including changing a height and a width of the cross-sectional, wherein a bottommost surface of the semiconductor fin remains in contact with the substrate; and
forming a transistor gate on the gate area of the semiconductor fin.
2. The method of claim 1 , wherein the changing of the cross-sectional area of the gate area of the semiconductor fin includes:
oxidizing an outer surface of the gate area of the semiconductor fin; and
stripping the oxidized outer surface from the gate area.
3. The method of claim 2 , wherein the oxidizing of the outer surface of the gate area includes a thermal oxidation.
4. The method of claim 2 , wherein the oxidizing of the outer surface of the gate area includes a wet oxidation.
5. The method of claim 1 , wherein, before the changing of the cross-sectional area of the gate area of the semiconductor fin, a cross-sectional area of the terminal area of the semiconductor fin is approximately equal to the cross-sectional area of the gate area of the semiconductor fin.
6. The method of claim 1 , wherein the changing of the cross-sectional area of the gate area includes a hydrochloric acid (HCl) etching of the semiconductor fin.
7. The method of claim 1 , wherein the changing of the cross-sectional area of the gate area of the semiconductor fin includes reducing the cross-sectional area of the gate area to increase a threshold voltage of the transistor gate on the gate area.
8. The method of claim 1 , wherein the changing of the cross-sectional area of the gate area of the semiconductor fin includes increasing the cross-sectional area of the gate area to reduce a threshold voltage of the transistor gate on the gate area.
9. The method of claim 1 , wherein a portion of the insulator is positioned on the sacrificial gate, wherein the removing of the sacrificial gate includes removing the portion of the insulator positioned on the sacrificial gate.
10. The method of claim 1 , further comprising:
forming a trench within the insulator to expose a portion of the doped semiconductor region on the terminal area of the semiconductor fin; and
forming a contact to the exposed portion of the terminal area of the semiconductor fin.
11. The method of claim 1 , wherein the changing of the cross-sectional area of the gate area includes epitaxially growing a semiconductor coating on the semiconductor fin.
12. The method of claim 11 , wherein the changing of the cross-sectional area of the gate area further includes annealing the semiconductor coating by one of thermal mixing and condensing.
13. The method of claim 1 , wherein the removing the sacrificial gate to expose the gate area of the semiconductor fin includes exposing a top surface of the fin.
14. A method comprising:
forming a structure including:
a semiconductor fin positioned on a substrate, wherein the semiconductor fin includes: a gate area having a first cross-sectional area, and a terminal area laterally distal to the gate area and having a second cross-sectional area, wherein the first cross-sectional area is approximately equal to the second cross-sectional area,
a sacrificial gate positioned on the gate area of the semiconductor fin, and
an insulator positioned on the terminal area of the semiconductor fin;
removing the sacrificial gate to expose the gate area of the semiconductor fin;
changing the first cross-sectional area of the gate area of the semiconductor fin, wherein the changing of the first cross-sectional area of the semiconductor fin increases or reduces a height and a width of the first cross-sectional area relative to the second cross-sectional area of the terminal area of the semiconductor fin, and wherein a bottommost surface of the semiconductor fin remains in contact with the substrate;
forming a transistor gate on the gate area of the semiconductor fin after the changing of the first cross-sectional area;
forming a trench within the insulator to expose a portion of the terminal area of the semiconductor fin, wherein the exposed portion of the terminal area of the semiconductor fin includes the second cross-sectional area;
forming a doped semiconductor region on the exposed portion of the terminal area of the semiconductor fin; and
forming a contact to the doped semiconductor region on the terminal area of the semiconductor fin.
15. The method of claim 14 , wherein the changing of the first cross-sectional area of the gate area of the semiconductor fin includes:
oxidizing an outer surface of the gate area of the semiconductor fin; and
stripping the oxidized outer surface from the gate area.
16. The method of claim 14 , wherein the changing of the first cross-sectional area of the gate area includes epitaxially growing a semiconductor coating on the semiconductor fin.
17. The method of claim 16 , wherein the changing of the first cross-sectional area of the gate area further includes annealing the semiconductor coating by one of thermal mixing and condensing.
18. A method comprising:
forming a structure including:
a semiconductor fin positioned on a substrate, wherein the semiconductor fin includes:
a gate area, and a terminal area laterally distal to the gate area,
a sacrificial gate positioned on the gate area of the semiconductor fin, and
an insulator positioned on the terminal area of the semiconductor fin;
removing the sacrificial gate to expose the gate area of the semiconductor fin;
after removing the sacrificial gate, changing a cross-sectional area of the gate area of the semiconductor fin including increasing a height and a width of the cross-sectional area by epitaxially growing a semiconductor coating on the gate area of the semiconductor fin; and
forming a transistor gate on the gate area of the semiconductor fin.