FINFET DEVICE AND METHOD OF MANUFACTURING
A method for producing a finFET having a fin with thinned sidewalls on a lower portion above a shallow trench isolation (STI) regions is provided. Embodiments include forming a fin surrounded by STI regions on a substrate; recessing the STI regions, revealing an upper portion of the fin; forming a spacer over side and upper surfaces of the upper portion of the fin; recessing the STI regions, exposing a lower portion of the fin; and thinning sidewalls of the lower portion of the fin.
1 . A device comprising:
a substrate;
a fin field-effect transistor (FinFET) on the substrate, wherein the fin includes a thinned region on sidewalls of a lower portion of the fin; and
a shallow trench isolation (STI) region below the thinned region of the lower portion of the fin.
2 . The device according to claim 1 , wherein the thinned region representing 5% to 70% of the overall fin height.
3 . The device according to claim 1 , wherein the thinned region extends into sides of the fin to a maximum depth of 5 nm.
4 . The device according to claim 1 , wherein the thinned region extends into sides of the fin to a minimum depth of 1 nm.
5 . The device according to claim 1 , wherein the thinned region is a semi-ellipsoid shape.
6 . The device according to claim 1 , wherein the STI region comprises an oxide.
7 . The device according to claim 1 , wherein the substrate comprises a silicon-on-insulator (SOI), or silicon-germanium (SiGe).
8 . The device according to claim 1 , further comprising:
a gate dielectric layer and gate electrode layer formed over the fin and STI region.
9 . The device according to claim 8 , wherein the gate dielectric layer and gate electrode layer together form a gate stack.
10 . The device according to claim 9 , wherein fin portions not under the gate stack are doped to form doped drain/source regions.
11 . The device according to claim 10 , wherein the source/drain regions are formed at opposite sides of the gate stack.
12 . A device comprising:
a fin formed on a semiconductor substrate; and
a shallow trench isolation (STI) region formed on sides of the fin,
wherein a lower portion of the fin, exposed above an upper surface of the STI region, includes a semi-ellipsoid shape in each side of the fin, the semi-ellipsoid shape having a depth of 1 to 5 nm into the sides of the fin.
13 . The device according to claim 12 , further comprising:
a gate dielectric layer and gate electrode layer formed over the fin and STI region.
14 . The device according to claim 13 , wherein the gate dielectric layer and gate electrode layer together form a gate stack.
15 . The device according to claim 12 , wherein the semi-ellipsoid shape represents 5% to 70% of the overall fin height.
16 . The device according to claim 14 , wherein fin portions not under the gate stack are doped to form doped drain/source regions.
17 . The device according to claim 16 , wherein the source/drain regions are formed at opposite sides of the gate stack.
18 . The device according to claim 12 , wherein the STI region comprises an oxide.
19 . The device according to claim 12 , wherein the semiconductor substrate comprises a silicon-on-insulator (SOI), or silicon-germanium (SiGe).
20 . A device comprising:
a fin formed on a semiconductor substrate;
a shallow trench isolation (STI) region formed on sides of the fin;
a gate dielectric layer and gate electrode layer formed as a gate stack over the fin and STI region;
source/drain regions formed on opposite sides of the gate stack,
wherein a lower portion of the fin, exposed above an upper surface of the STI region, includes a semi-ellipsoid shape in each side of the fin, the semi-ellipsoid shape having a depth of 1 to 5 nm into the sides of the fin, and
wherein the semi-ellipsoid shape represents 5% to 70% of the overall fin height.