Spacers for tight gate pitches in field effect transistors
Structures for spacers of a field-effect transistor and methods for forming such spacers. A mask layer has a feature separated from a vertical sidewall of a first gate structure by a space of predetermined width that exposes a top surface of a semiconductor body. A spacer is formed adjacent to the vertical sidewall of the first gate structure. The spacer has a first section in the space and a second section. The first section of the spacer is located vertically between the second section of the spacer and the top surface of the semiconductor body. The first section of the spacer extends through the space to the top surface of the semiconductor body, and the first section of the spacer fully fills the space.
1. A structure comprising:
a semiconductor body having a top surface;
an epitaxial layer of semiconductor material on the semiconductor body;
a first gate structure on the semiconductor body, the first gate structure having a sidewall;
a first spacer adjacent to the sidewall of the first gate structure, the first spacer having a first section and a second section vertically between the first section and the top surface of the semiconductor body, the first section of the first spacer having a first thickness, and the second section of the first spacer having a second thickness different from the first thickness; and
a conformal layer on the first spacer and the epitaxial layer of semiconductor material,
wherein the second section of the first spacer is located between the epitaxial layer of semiconductor material and the sidewall of the first gate structure, the first spacer is composed of SiBCN having a first dielectric constant, and the conformal layer is composed of SiBCN having a second dielectric constant that is less than the first dielectric constant of the SiBCN of the first spacer.
2. The structure of claim 1 wherein the second thickness of the second section of the first spacer is greater than the first thickness of the first section of the first spacer.
3. The structure of claim 1 wherein the second section of the first space fully fills a space between the epitaxial layer of semiconductor material and the sidewall of the first gate structure.
4. The structure of claim 1 further comprising:
a second gate structure on the semiconductor body, the second gate structure having a sidewall,
wherein the first spacer and the epitaxial layer of semiconductor material are positioned between the sidewall of the first gate structure and the sidewall of the second gate structure.
5. The structure of claim 4 further comprising:
a second spacer between the epitaxial layer of semiconductor material and the sidewall of the second gate structure, the second spacer having a first section and a second section vertically between the first section and the top surface of the semiconductor body, the first section of the second spacer having a first thickness, and the second section of the second spacer having a second thickness that is different than the first thickness.
6. The structure of claim 1 wherein the second section of the first spacer is in contact with the top surface of the semiconductor body.
7. The structure of claim 1 wherein the first section of the first spacer extends over a majority of a height of the first gate structure.
8. The structure of claim 1 wherein the semiconductor body is a semiconductor fin.
9. A structure comprising:
a semiconductor body having a top surface;
a gate structure on the semiconductor body, the gate structure having a sidewall;
a first spacer adjacent to the sidewall of the gate structure, the first spacer having a first section and a second section vertically between the first section and the top surface of the semiconductor body, the first section of the first spacer having a first thickness, and the second section of the first spacer having a second thickness different from the first thickness; and
a second spacer adjacent to the sidewall of the gate structure,
wherein the first spacer is arranged between the second spacer and the sidewall of the gate structure, the first spacer has a first dielectric constant, the second spacer has a second dielectric constant that is less than the first dielectric constant, the first spacer is composed of SiBCN having a first dielectric constant, and the second spacer is composed of SiBCN having a second dielectric constant that is less than the first dielectric constant of the SiBCN of the first spacer.
10. The structure of claim 9 wherein the second section of the first spacer is in contact with the top surface of the semiconductor body.
11. The structure of claim 9 wherein the first section of the first spacer extends over a majority of a height of the gate structure.
12. The structure of claim 9 wherein the semiconductor body is a semiconductor fin.
13. The structure of claim 9 wherein the second thickness of the second section of the first spacer is greater than the first thickness of the first section of the first spacer.