Spacers for tight gate pitches in field effect transistors
Structures for spacers of a field-effect transistor and methods for forming such spacers. A mask layer has a feature separated from a vertical sidewall of a first gate structure by a space of predetermined width that exposes a top surface of a semiconductor body. A spacer is formed adjacent to the vertical sidewall of the first gate structure. The spacer has a first section in the space and a second section. The first section of the spacer is located vertically between the second section of the spacer and the top surface of the semiconductor body. The first section of the spacer extends through the space to the top surface of the semiconductor body, and the first section of the spacer fully fills the space.
1. A method comprising:
forming a mask layer having a feature separated from a vertical sidewall of a first gate structure by a space of predetermined width that exposes a top surface of a semiconductor body;
forming a spacer adjacent to the vertical sidewall of the first gate structure, the spacer having a first section in the space and a second section; and
after forming the spacer, removing the feature of the mask layer,
wherein the mask layer is composed of a dielectric material, the first section of the spacer is located vertically between the second section of the spacer and the top surface of the semiconductor body, the first section of the spacer extends through the space to the top surface of the semiconductor body, and the first section of the spacer fully fills the space.
2. The method of claim 1 wherein the second section of the spacer has a thickness, and the first section of the spacer has a thickness that is greater than the thickness of the second section of the spacer.
3. The method of claim 1 further comprising;
removing the first gate structure; and
forming a gate electrode to replace the first gate structure,
wherein the spacer is located in the space adjacent to a vertical sidewall of the gate electrode.
4. The method of claim 1 wherein the first section of the spacer is in contact with the top surface of the semiconductor body.
5. The method of claim 1 wherein the second section of the spacer extends over a majority of a height of the first gate structure.
6. The method of claim 1 wherein the semiconductor body is a semiconductor fin.
7. The method of claim 1 wherein the dielectric material is silicon dioxide.
8. A method comprising:
forming a mask layer having a feature separated from a vertical sidewall of a first gate structure by a space of predetermined width that exposes a top surface of a semiconductor body;
forming a spacer adjacent to the vertical sidewall of the first gate structure, the spacer having a first section in the space and a second section;
after forming the spacer, removing the feature of the mask layer; and
after removing the feature of the mask layer, removing the portion of the first conformal layer covered by the feature of the mask layer to expose the top surface of the semiconductor body,
wherein the first section of the spacer is located vertically between the second section of the spacer and the top surface of the semiconductor body, the first section of the spacer extends through the space to the top surface of the semiconductor body, and the first section of the spacer fully fills the space; and
wherein forming the mask layer having the feature separated by the space of the predetermined width that extends to the top surface of the semiconductor body comprises:
depositing a first conformal layer on the vertical sidewall of the first gate structure and on the top surface of the semiconductor body in the space adjacent to the vertical sidewall of the first gate structure;
covering a portion of the first conformal layer located on the top surface of the semiconductor body with the feature of the mask layer; and
removing the first conformal layer from the vertical sidewall of the first gate structure to open the space between the first gate structure and the mask that extends to the top surface of the semiconductor body.
9. The method of claim 8 wherein the first conformal layer has a thickness, the predetermined width is equal to the thickness of the first conformal layer, and the first section of the spacer has a thickness that is equal to the thickness of the first conformal layer.
10. The method of claim 8 further comprising:
growing an epitaxial layer of semiconductor material on the top surface of the semiconductor body,
wherein the first section of the spacer is located between the epitaxial layer of semiconductor material and the vertical sidewall of the first gate structure.
11. The method of claim 8 wherein the portion of the first conformal layer is located between the vertical sidewall of the first gate structure and a vertical sidewall of a second gate structure.
12. The method of claim 11 wherein covering the portion of the first conformal layer located on the top surface of the semiconductor body with the mask comprises:
depositing a gap-fill layer between the first gate structure and the second gate structure to define the mask.
13. The method of claim 12 wherein the first conformal layer has a thickness, the gap-fill layer has a thickness, and the first section of the spacer has a vertical height that is equal to a sum of the thickness of the first conformal layer and the thickness of the gap-fill layer.
14. The method of claim 8 wherein the mask layer is composed of a dielectric material.
15. The method of claim 14 wherein the dielectric material is silicon dioxide.
16. A method comprising:
forming a mask layer having a feature separated from a vertical sidewall of a first gate structure by a space of predetermined width that exposes a top surface of a semiconductor body;
forming a spacer adjacent to the vertical sidewall of the first gate structure, the spacer having a first section in the space and a second section;
after forming the spacer, removing the feature of the mask layer; and
after removing the feature of the mask layer, growing an epitaxial layer of semiconductor material on the top surface of the semiconductor body,
wherein the first section of the spacer is located vertically between the second section of the spacer and the top surface of the semiconductor body, the first section of the spacer extends through the space to the top surface of the semiconductor body, the first section of the spacer fully fills the space, and the first section of the spacer is located between the epitaxial layer of semiconductor material and the vertical sidewall of the first gate structure.
17. The method of claim 16 further comprising:
depositing a second conformal layer that covers the spacer and the epitaxial layer of semiconductor material,
wherein the spacer is arranged between the second conformal layer and the vertical sidewall of the gate structure.
18. The method of claim 17 wherein the spacer is composed of SiBCN, and the second conformal layer is composed of SiBCN with a lower dielectric constant than the SiBCN of the spacer.
19. The method of claim 16 wherein the mask layer is composed of a dielectric material.
20. The method of claim 19 wherein the dielectric material is silicon dioxide.