FIELD EFFECT TRANSISTOR STRUCTURE WITH RECESSED INTERLAYER DIELECTRIC AND METHOD
Disclosed are a field effect transistor (FET) and a FET formation method. In the FET, an interlayer dielectric (ILD) layer is positioned laterally adjacent to a sidewall spacer of a replacement metal gate and a cap layer covers the ILD layer, the sidewall spacer and the gate. However, during processing after the gate is formed but before the cap layer is formed, the ILD layer is polished and then recessed such that the top surface of the ILD layer is lower than the top surfaces of the sidewall spacer and the gate. The cap layer is then deposited such that the cap layer is, not only above the top surfaces of the ILD layer, sidewall spacer and gate, but also positioned laterally adjacent to a vertical surface of the sidewall spacer. Recessing the ILD layer prevents shorts between the gate and subsequently formed contacts to the FET source/drain regions.
1 . A field effect transistor comprising:
source/drain regions and a channel region positioned laterally between the source/drain regions;
a gate adjacent to the channel region;
a sidewall spacer positioned laterally adjacent to a sidewall of the gate;
an interlayer dielectric layer positioned laterally adjacent to the sidewall spacer, the interlayer dielectric layer having a top surface that is at a lower level than top surfaces of the gate and the sidewall spacer; and
a dielectric cap layer on the interlayer dielectric layer, the sidewall spacer and gate, the dielectric cap layer having a portion above the top surface of the interlayer dielectric layer and positioned laterally immediately adjacent to a vertical surface of the sidewall spacer.
2 . The field effect transistor of claim 1 , the gate comprising a replacement metal gate and the field effect transistor further comprising:
an additional interlayer dielectric layer on the dielectric cap layer; and
contacts that extend vertically through the additional interlayer dielectric layer, the dielectric cap layer and the interlayer dielectric layer to source/drain regions.
3 . The field effect transistor of claim 1 , the top surface of the interlayer dielectric layer being separated from the top surfaces of the gate and the sidewall spacer by a distance of approximately 2-4 nm.
4 . The field effect transistor of claim 1 , the interlayer dielectric layer being devoid of micro-scratches.
5 . The field effect transistor of claim 1 , wherein any movement of metal along an interface between the interlayer dielectric layer and the dielectric cap layer is blocked by the sidewall spacer.
6 . The field effect transistor of claim 1 , the interlayer dielectric layer comprising a silicon dioxide layer and the dielectric cap layer comprising a silicon nitride layer.
7 . A field effect transistor comprising:
source/drain regions and a channel region positioned laterally between the source/drain regions;
a gate adjacent to the channel region, wherein the gate has a first top surface and a first sidewall;
a sidewall spacer positioned laterally adjacent to the first sidewall of the gate, wherein the sidewall spacer has a second sidewall and a second top surface;
an interlayer dielectric layer positioned laterally adjacent to the second sidewall of the sidewall spacer, the interlayer dielectric layer having a third top surface that is below a level of the first top surface and the second top surface; and
a dielectric cap layer on the interlayer dielectric layer, the sidewall spacer and gate, wherein the dielectric cap layer has an essentially uniform thickness and a portion that is above the third top surface of the interlayer dielectric layer, that is positioned laterally immediately adjacent to the second sidewall of the sidewall spacer and that has a fourth top surface below a level of the first top surface of the gate.
8 . The field effect transistor of claim 7 , the gate comprising a replacement metal gate and the field effect transistor further comprising:
an additional interlayer dielectric layer on the dielectric cap layer; and
contacts that extend vertically through the additional interlayer dielectric layer, the dielectric cap layer and the interlayer dielectric layer to source/drain regions.
9 . The field effect transistor of claim 7 , the third top surface of the interlayer dielectric layer is separated from the first top surface of the gate and the second top surface of the sidewall spacer by a distance of approximately 2-4 nm.
10 . The field effect transistor of claim 7 , the interlayer dielectric layer being devoid of micro-scratches.
11 . The field effect transistor of claim 7 , wherein any movement of metal along an interface between the interlayer dielectric layer and the dielectric cap layer is blocked by the sidewall spacer.
12 . The field effect transistor of claim 7 , the interlayer dielectric layer comprising a silicon dioxide layer and the dielectric cap layer comprising a silicon nitride layer.
13 . A field effect transistor comprising:
source/drain regions and a channel region positioned laterally between the source/drain regions;
a gate adjacent to the channel region, wherein the gate has a first top surface and a first sidewall;
a sidewall spacer positioned laterally adjacent to the first sidewall of the gate, wherein the sidewall spacer has a second sidewall and a second top surface and wherein the first top surface of the gate and the second top surface of the sidewall spacer are essentially co-planar;
an interlayer dielectric layer positioned laterally adjacent to the second sidewall of the sidewall spacer, the interlayer dielectric layer having a third top surface that is below a level of the first top surface and the second top surface; and
a dielectric cap layer on the interlayer dielectric layer, the sidewall spacer and gate, wherein the dielectric cap layer has an essentially uniform thickness and a portion that is above the third top surface of the interlayer dielectric layer, that is positioned laterally immediately adjacent to the second sidewall of the sidewall spacer and that has a fourth top surface below a level of the first top surface of the gate.
14 . The field effect transistor of claim 13 , the gate comprising a replacement metal gate and the field effect transistor further comprising:
an additional interlayer dielectric layer on the dielectric cap layer; and
contacts that extend vertically through the additional interlayer dielectric layer, the dielectric cap layer and the interlayer dielectric layer to source/drain regions.
15 . The field effect transistor of claim 13 , the third top surface of the interlayer dielectric layer is separated from the first top surface of the gate and the second top surface of the sidewall spacer by a distance of approximately 2-4 nm.
16 . The field effect transistor of claim 13 , the interlayer dielectric layer being devoid of micro-scratches.
17 . The field effect transistor of claim 13 , wherein any movement of metal along an interface between the interlayer dielectric layer and the dielectric cap layer is blocked by the sidewall spacer.
18 . The field effect transistor of claim 13 , the interlayer dielectric layer comprising a silicon dioxide layer and the dielectric cap layer comprising a silicon nitride layer.