Transistor device structures with retrograde wells in CMOS applications
A device includes a substrate having an N-active region and a P-active region, a layer of silicon-carbon positioned on an upper surface of the N-active region, a first layer of a first semiconductor material positioned on the layer of silicon-carbon, a second layer of the first semiconductor material positioned on an upper surface of the P-active region, and a layer of a second semiconductor material positioned on the second layer of the first semiconductor material. An N-type transistor is positioned in and above the N-active region and a P-type transistor is positioned in and above the P-active region.
1. A device, comprising:
a substrate comprising an N-active region and a P-active region;
a layer of silicon-carbon positioned on an upper surface of said N-active region but not on an upper surface of said P-active region;
a first layer of a first semiconductor material positioned on said layer of silicon-carbon, wherein an upper surface of said first layer of said first semiconductor material is substantially level with an upper surface of an isolation region defining said N-active region;
a second layer of said first semiconductor material positioned on said upper surface of said P-active region;
a layer of a second semiconductor material positioned on said second layer of said first semiconductor material;
an N-type transistor positioned in and above said N-active region; and
a P-type transistor positioned in and above said P-active region.
2. The device of claim 1 , wherein said first semiconductor material comprises silicon.
3. The device of claim 1 , wherein said second semiconductor material comprises one of a silicon-germanium material and a III-V material.
4. The device of claim 1 , wherein a thickness of said layer of silicon-carbon falls within a range of approximately 5-10 nm.
5. The device of claim 1 , wherein said N-type transistor is one of a planar transistor and a FinFET transistor, and wherein said P-type transistor is one of a planar transistor and a FinFET transistor.
6. The device of claim 1 , wherein said upper surface of said N-active region and said upper surface of said P-active region are recessed relative to an upper surface of an isolation region separating said N-active region and said P-active region.
7. The device of claim 1 , wherein an upper surface of said layer of said second semiconductor material is substantially level with an upper surface of an isolation region defining said P-active region.
8. A device, comprising:
a substrate comprising an N-active region and a P-active region;
a layer of silicon-carbon positioned on and in direct contact with a recessed upper surface of said N-active region;
a first layer of silicon positioned on said layer of silicon-carbon;
a second layer of silicon positioned on and in direct contact with a recessed upper surface of said P-active region;
a layer of a first semiconductor material positioned on said second layer of silicon, said first semiconductor material comprising silicon-germanium, wherein an upper surface of said layer of said first semiconductor material is substantially level with an upper surface of an isolation region defining said P-active region;
an N-type transistor positioned in and above said N-active region; and
a P-type transistor positioned in and above said P-active region.
9. The device of claim 8 , wherein a thickness of said layer of silicon-carbon falls within a range of approximately 5-10 nm.
10. The device of claim 8 , wherein said N-type transistor is one of a planar transistor and a FinFET transistor, and wherein said P-type transistor is one of a planar transistor and a FinFET transistor.
11. The device of claim 8 , wherein an upper surface of said first layer of silicon is substantially level with an upper surface of an isolation region defining said N-active region.
12. A device, comprising:
a first isolation region positioned in a substrate, said first isolation region defining an N-active region having an upper surface that is recessed relative to an upper surface of said first isolation region;
a layer of silicon-carbon positioned on and in direct contact with said recessed upper surface of said N-active region;
a first layer of a first semiconductor material positioned on said layer of silicon-carbon, wherein an upper surface of said first layer of said first semiconductor material is substantially level with said upper surface of said first isolation region;
a second isolation region positioned in said substrate, said second isolation region defining a P-active region having an upper surface that is recessed relative to an upper surface of said second isolation region;
a second layer of said first semiconductor material positioned on and in direct contact with said recessed upper surface of said P-active region;
a layer of a second semiconductor material positioned on said second layer of said first semiconductor material, wherein an upper surface of said layer of said second semiconductor material is substantially level with said upper surface of said second isolation region;
an N-type transistor positioned in and above said N-active region; and
a P-type transistor positioned in and above said P-active region.
13. The device of claim 12 , wherein a thickness of said layer of silicon-carbon falls within a range of approximately 5-10 nm.
14. The device of claim 12 , wherein said N-type transistor is one of a planar transistor and a FinFET transistor, and wherein said P-type transistor is one of a planar transistor and a FinFET transistor.
15. The device of claim 12 , wherein said first semiconductor material comprises silicon.
16. The device of claim 12 , wherein said second semiconductor material comprises one of a silicon-germanium material and a III-V material.