Methods of forming transistors with retrograde wells in CMOS applications and the resulting device structures
One illustrative method disclosed herein includes performing a first plurality of epitaxial deposition processes to form a first plurality of semiconductor materials selectively above the N-active region while masking the P-active region, performing a second plurality of epitaxial deposition processes to form a second plurality of semiconductor materials selectively above the P-active region while masking the N-active region, forming an N-type transistor in and above the N-active region and forming a P-type transistor in and above the P-active region.
1. A method, comprising:
forming an N-active region and a P-active region in a semiconductor substrate;
performing a common etching process to form recesses in said N-active region and said P-active region such that said N-active region and said P-active region have recessed surfaces;
performing a first plurality of epitaxial deposition processes to form a first plurality of semiconductor materials selectively above said N-active region while masking said P-active region, wherein performing said first plurality of epitaxial deposition processes comprises forming a layer of silicon-carbon on said recessed surface of said N-active region and forming a first layer of a first semiconductor material on said layer of silicon-carbon;
performing a second plurality of epitaxial deposition processes to form a second plurality of semiconductor materials selectively above said P-active region while masking said N-active region, wherein performing said second plurality of epitaxial deposition processes comprises forming a second layer of said first semiconductor material on said recessed surface of said P-active region and forming a layer of a second semiconductor material on said second layer of said first semiconductor material, wherein said first semiconductor material is a different semiconductor material from said second semiconductor material;
forming an N-type transistor in and above said N-active region; and
forming a P-type transistor in and above said P-active region.
2. The method of claim 1 , wherein said first semiconductor material comprises silicon.
3. The method of claim 2 , wherein said second semiconductor material comprises silicon-germanium or a III-V material.
4. The method of claim 1 , wherein said second semiconductor material comprises silicon-germanium or a III-V material.
5. The method of claim 1 , wherein said N-active region is defined by a first isolation region positioned in said substrate and said P-active region is defined by a second isolation region positioned in said substrate, and wherein:
at least one of said first plurality of epitaxial deposition processes is performed such that an upper surface of said first layer of said first semiconductor material that is formed on said layer of silicon-carbon is substantially level with an upper surface of said first isolation region; and
at least one of said second plurality of epitaxial deposition processes is performed such that an upper surface of said layer of said second semiconductor material formed on said second layer of said first semiconductor material is substantially level with an upper surface of said second isolation region.
6. The method of claim 1 , wherein said first plurality of epitaxial deposition processes are performed prior to performing said second plurality of epitaxial deposition processes.
7. The method of claim 1 , wherein said second plurality of epitaxial deposition processes are performed prior to performing said first plurality of epitaxial deposition processes.
8. A method, comprising:
forming an N-active region and a P-active region in a semiconductor substrate;
performing a common etching process to form recesses in said N-active region and said P-active region such that said N-active region and said P-active region have recessed surfaces;
forming a first masking layer that covers said N-active region while leaving an area above said P-active region un-masked;
with said first masking layer in position, forming a first layer of a first semiconductor material on said recessed surface of said P-active region and forming a layer of a second semiconductor material on said first layer of said first semiconductor material, wherein said first semiconductor material is a different semiconductor material from said second semiconductor material;
removing said first masking layer;
after forming said layer of said second semiconductor material on said first layer of said first semiconductor material and removing said first masking layer, forming a second masking layer that covers said P-active region while leaving an area above said N-active region un-masked;
with said second masking layer in position, forming a layer of silicon-carbon on said recessed surface of said N-active region and forming a second layer of said first semiconductor material on said layer of silicon-carbon;
removing said second masking layer;
forming an N-type transistor in and above said N-active region; and
forming a P-type transistor in and above said P-active region.
9. The method of claim 8 , wherein said first semiconductor material comprises silicon.
10. The method of claim 9 , wherein said second semiconductor material comprises silicon-germanium or a III-V material.
11. The method of claim 8 , wherein said second semiconductor material comprises silicon-germanium or a III-V material.
12. The method of claim 8 , wherein said N-active region is defined by a first isolation region positioned in said substrate and said P-active region is defined by a second isolation region positioned in said substrate, and wherein:
said layer of said second semiconductor material is formed above said P-active region such that an upper surface of said layer of said second semiconductor material is substantially level with an upper surface of said second isolation region; and
said layer of said second semiconductor material is formed above said N-active region such that an upper surface of said layer of said second semiconductor material is substantially level with an upper surface of said first isolation region.
13. The method of claim 8 wherein said first layer of said first semiconductor material is formed on and in contact with said recessed surface of said P-active region, said layer of said second semiconductor material is formed on and in contact with said first layer of said first semiconductor material, said layer of silicon-carbon is formed on and in contact with said recessed surface of said N-active region and said second layer of said first semiconductor material is formed on and in contact with said layer of silicon-carbon.
14. A method, comprising:
forming an N-active region and a P-active region in a semiconductor substrate;
performing a common etching process to form recesses in said N-active region and said P-active region such that said N-active region and said P-active region have recessed surfaces;
forming a first masking layer that covers said P-active region while leaving an area above said N-active region un-masked;
with said first masking layer in position, forming a layer of silicon-carbon on said recessed surface of said N-active region and forming a first layer of a first semiconductor material on said layer of silicon-carbon;
removing said first masking layer;
after forming said first layer of said first semiconductor material on said layer of silicon-carbon and removing said first masking layer, forming a second masking layer that covers said N-active region while leaving an area above said P-active region un-masked;
with said second masking layer in position, forming a second layer of said first semiconductor material on said recessed surface of said P-active region and forming a layer of a second semiconductor material on said second layer of said first semiconductor material, wherein said first semiconductor material is a different semiconductor material from said second semiconductor material;
removing said second masking layer;
forming an N-type transistor in and above said N-active region; and
forming a P-type transistor in and above said P-active region.
15. The method of claim 14 , wherein said first semiconductor material comprises silicon.
16. The method of claim 15 , wherein said second semiconductor material comprises silicon-germanium or a III-V material.
17. The method of claim 14 , wherein said second semiconductor material comprises silicon-germanium or a III-V material.
18. The method of claim 14 , wherein said N-active region is defined by a first isolation region positioned in said substrate and said P-active region is defined by a second isolation region positioned in said substrate, and wherein:
said layer of said second semiconductor material is formed above said P-active region such that an upper surface of said layer of said second semiconductor material is substantially level with an upper surface of said second isolation region; and
said layer of said second semiconductor material is formed above said N-active region such that an upper surface of said layer of said second semiconductor material is substantially level with an upper surface of said first isolation region.
19. The method of claim 14 , wherein said layer of silicon-carbon is formed on and in contact with said recessed surface of said N-active region, said first layer of said first semiconductor material is formed on and in contact with said layer of silicon-carbon, said second layer of said first semiconductor material is formed on and in contact with said recessed surface of said P-active region, and said layer of said second semiconductor material is formed on and in contact with said second layer of said first semiconductor material.