Methods of forming transistors with retrograde wells in CMOS applications and the resulting device structures
A method includes forming a layer of silicon-carbon on an N-active region, performing a common deposition process to form a layer of a first semiconductor material on the layer of silicon-carbon and on the P-active region, masking the N-active region, forming a layer of a second semiconductor material on the first semiconductor material in the P-active region and forming N-type and P-type transistors. A device includes a layer of silicon-carbon positioned on an N-active region, a first layer of a first semiconductor positioned on the layer of silicon-carbon, a second layer of the first semiconductor material positioned on a P-active region, a layer of a second semiconductor material positioned on the second layer of the first semiconductor material, and N-type and P-type transistors.
1. A method, comprising:
forming an N-active region and a P-active region in a semiconductor substrate;
forming a first masking layer that covers said P-active region while leaving an area above said N-active region un-masked;
with said first masking layer in position, forming a layer of silicon-carbon on an upper surface of said N-active region;
removing said first masking layer;
performing a common deposition process to form a first portion of a layer of a first semiconductor material on said layer of silicon-carbon and a second portion of said first semiconductor material on an upper surface of said P-active region;
forming a second masking layer that covers said N-active region while leaving an area above said P-active region un-masked;
with said second masking layer in position, forming a layer of a second semiconductor material on said second portion of said first semiconductor material;
removing said second masking layer;
forming an N-type transistor in and above said N-active region; and
forming a P-type transistor in and above said P-active region.
2. The method of claim 1 , wherein said first semiconductor material is comprised of silicon.
3. The method of claim 1 , wherein said second semiconductor material is comprised of silicon-germanium or a III-V material.
4. The method of claim 2 , wherein said second semiconductor material is comprised of silicon-germanium or a III-V material.
5. The method of claim 1 , wherein prior to forming said first masking layer, the method further comprises performing a common etching process to form recesses in said N-active region and said P-active region.
6. The method of claim 1 , wherein said N-type transistor and said P-type transistor are planar transistors or FinFET transistors.
7. The method of claim 1 , wherein said N-active region is defined by a first isolation region positioned in said substrate and said P-active region is defined by a second isolation region positioned in said substrate, and wherein the method further comprises:
performing said common deposition process such that an upper surface of said first portion of said layer of a first semiconductor material is substantially level with an upper surface of said first isolation region; and
forming said layer of said second semiconductor material is performed such that an upper surface of said layer of said second semiconductor material is substantially level with an upper surface of said second isolation region.
8. A method, comprising:
forming an N-active region and a P-active region in a semiconductor substrate;
performing a common etching process to form recesses in said N-active region and said P-active region such that said N-active region and said P-active region have recessed surfaces;
forming a first masking layer that covers said P-active region while leaving an area above said N-active region un-masked;
with said first masking layer in position, forming a layer of silicon-carbon on said recessed surface of said N-active region;
removing said first masking layer;
performing a common deposition process to form a first portion of a layer of silicon on said layer of silicon-carbon and a second portion of said layer of silicon on said recessed surface of said P-active region;
forming a second masking layer that covers said N-active region while leaving an area above said P-active region un-masked;
with said second masking layer in position, forming a layer of a first semiconductor material on said second portion of said layer of silicon;
removing said second masking layer;
forming an N-type transistor in and above said N-active region; and
forming a P-type transistor in and above said P-active region.
9. The method of claim 8 , wherein said second semiconductor material is comprised of silicon-germanium or a III-V material.
10. The method of claim 8 , wherein said N-active region is defined by a first isolation region positioned in said substrate and said P-active region is defined by a second isolation region positioned in said substrate, and wherein the method further comprises:
performing said common deposition process such that an upper surface of said first portion of said layer of silicon is substantially level with an upper surface of said first isolation region; and
forming said layer of said first semiconductor material is performed such that an upper surface of said layer of said first semiconductor material is substantially level with an upper surface of said second isolation region.