Method to improve crystalline regrowth
The migration of dislocations into pristine single crystal material during crystal growth of an adjacent conductive strap is inhibited by a conductive barrier formed at the interface between the layers. The conductive barrier may be formed by implanting carbon impurities or depositing Si:C layer that inhibits dislocation movement across the barrier layer, or by forming a passivation layer by annealing in vacuum prior to deposition of amorphous Si to prevent polycrystalline nucleation at the surface of single crystalline Si, or by implanting nucleation promoting species to enhance the nucleation of polycrystalline Si away from single crystalline Si.
1. A semiconductor device comprising:
a conductive strap electrically connecting an electrode with a single crystal region of a semiconductor substrate; and
a conductive barrier layer between the conductive strap and the single crystal region,
wherein the conductive barrier layer comprises carbon, hydrogen, cobalt or titanium nitride, and at least one of germanium and phosphorus.
2. The semiconductor device of claim 1 , wherein the conductive strap comprises polycrystalline silicon.
3. The semiconductor device of claim 1 , wherein the electrode comprises polycrystalline silicon.
4. The semiconductor device of claim 1 , wherein the conductive barrier layer thickness is from 0.1 to 10 nm.
5. The semiconductor device of claim 1 , wherein the conductive barrier layer comprises carbon-doped silicon.
6. A deep trench capacitor in a semiconductor substrate, comprising:
a buried plate disposed about an exterior portion of a trench located within the substrate;
a node dielectric disposed over the buried plate;
an electrode disposed over the node dielectric;
a conductive strap electrically connected to the electrode and a single crystal region of the substrate; and
a conductive barrier layer between the conductive strap and the single crystal region,
wherein the conductive barrier layer comprises carbon, hydrogen, cobalt or titanium nitride, and at least one of germanium and phosphorus.
7. The deep trench capacitor of claim 6 , wherein the conductive strap comprises polycrystalline silicon.
8. The deep trench capacitor of claim 6 , wherein the electrode comprises polycrystalline silicon.
9. The deep trench capacitor of claim 6 , wherein the conductive barrier layer thickness is from 0.1 to 10 nm.
10. The deep trench capacitor of claim 6 , wherein the conductive barrier layer comprises carbon-doped silicon.