Self-aligned finFET formation
A method for fabricating a semiconductor device comprises forming a first hardmask, a planarizing layer, and a second hardmask on a substrate. Removing portions of the second hardmask and forming alternating blocks of a first material and a second material over the second hardmask. The blocks of the second material are removed to expose portions of the planarizing layer. Exposed portions of the planarizing layer and the first hardmask are removed to expose portions of the first hardmask. Portions of the first hardmask and portions of the substrate are removed to form a first fin and a second fin. Portions of the substrate are removed to further increase the height of the first fin and substantially remove the second fin. A gate stack is formed over a channel region of the first fin.
1. A method for fabricating a semiconductor device, the method comprising:
forming a first hardmask on a semiconductor substrate;
forming a planarizing layer on the first hardmask;
forming a second hardmask on the planarizing layer;
removing portions of the second hardmask;
forming alternating vertical blocks of a first material and a second material over the second hardmask;
removing the vertical blocks of the second material to expose portions of the planarizing layer;
removing exposed portions of the planarizing layer to expose portions of the first hardmask and removing portions of the first hardmask to expose portions of the semiconductor substrate;
removing exposed portions of the semiconductor substrate to form a first fin and a second fin, wherein the first fin is arranged under a portion of the planarizing layer;
further removing exposed portions of the semiconductor substrate to further increase the height of the first fin and substantially remove the second fin;
forming a gate stack over a channel region of the first fin; and
depositing a layer of the first material over portions of a first layer of the second hardmask prior to forming the alternating vertical blocks of the first material and the second material.
2. The method of claim 1 , wherein the second hardmask includes a first layer arranged on the planarizing layer, a second layer arranged on the first layer, and a third layer arranged on the second layer.
3. The method of claim 2 , wherein the first layer of the second hardmask includes a nitride material.
4. The method of claim 2 , wherein the second layer of the second hardmask includes an oxide material.
5. The method of claim 2 , wherein the third layer of the second hardmask includes a polymer material.
6. The method of claim 1 , wherein the first hardmask is a nitride material.
7. The method of claim 1 , wherein the planarizing layer includes an organic planarizing material.
8. The method of claim 1 , wherein the first material includes a polystyrene material.
9. The method of claim 1 , wherein the second material includes a poly(methyl methacrylate) (PMMA) material.
10. The method of claim 1 , wherein the second hardmask comprises more than one layer.
11. The method of claim 1 , wherein the second hardmask comprises a stack of layers.
12. The method of claim 1 , wherein the second hardmask comprises a stack of at least two different layers.
13. The method of claim 1 , wherein the second hardmask comprises a stack of three layers.
14. The method of claim 13 , wherein the three layers are different materials.
15. The method of claim 1 , wherein the substrate comprises silicon.
16. A method for fabricating a semiconductor device, the method comprising:
forming a first hardmask on a semiconductor substrate;
forming a planarizing layer on the first hardmask;
forming a second hardmask on the planarizing layer;
removing portions of the second hardmask;
forming alternating vertical blocks of a first material and a second material over the second hardmask;
removing the vertical blocks of the second material to expose portions of the planarizing layer;
removing exposed portions of the planarizing layer to expose portions of the first hardmask and removing portions of the first hardmask to expose portions of the semiconductor substrate;
removing exposed portions of the semiconductor substrate to form a first fin and a second fin, wherein the first fin is arranged under a portion of the planarizing layer;
further removing exposed portions of the semiconductor substrate to further increase the height of the first fin and substantially remove the second fin; and
forming a gate stack over a channel region of the first fin;
wherein at least a part of the first fin has a sloped profile.
17. The method of claim 16 , wherein the sloped profile is formed in proximity to the second fin.