IP Library Granted Patent US 10,170,591
Granted Patent B2
US 10,170,591 · App. 15/178,871 · Granted Jan 1, 2019

Self-aligned finFET formation

Inventors: Cheng Chi (Jersey City, NJ); Fee Li Lie (Albany, NY); Chi-Chun Liu (Altamont, NY); Ruilong Xie (Schenectady, NY)
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
H01L29/66795H01L21/0332H01L21/0337H01L21/31051H01L21/823431H01L27/0886H01L29/0649H01L29/7851
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Quick Facts
Patent No.
US 10,170,591
App. No.
15/178,871
Granted
Jan 1, 2019
Kind
B2
Abstract

A method for fabricating a semiconductor device comprises forming a first hardmask, a planarizing layer, and a second hardmask on a substrate. Removing portions of the second hardmask and forming alternating blocks of a first material and a second material over the second hardmask. The blocks of the second material are removed to expose portions of the planarizing layer. Exposed portions of the planarizing layer and the first hardmask are removed to expose portions of the first hardmask. Portions of the first hardmask and portions of the substrate are removed to form a first fin and a second fin. Portions of the substrate are removed to further increase the height of the first fin and substantially remove the second fin. A gate stack is formed over a channel region of the first fin.

Claims (41)

1. A method for fabricating a semiconductor device, the method comprising:

forming a first hardmask on a semiconductor substrate;

forming a planarizing layer on the first hardmask;

forming a second hardmask on the planarizing layer;

removing portions of the second hardmask;

forming alternating blocks of a first material and a second material over the second hardmask;

removing the blocks of the second material to expose portions of the planarizing layer;

removing exposed portions of the planarizing layer to expose portions of the first hardmask and removing portions of the first hardmask to expose portions of the semiconductor substrate;

removing exposed portions of the semiconductor substrate to form a first fin and a second fin, wherein the first fin is arranged under a portion of the planarizing layer;

further removing exposed portions of the semiconductor substrate to further increase the height of the first fin and substantially remove the second fin; and

forming a gate stack over a channel region of the first fin;

wherein the planarizing layer includes an organic planarizing material;

wherein the second hardmask includes a first layer arranged on the planarizing layer, a second layer arranged on the first layer, and a third layer arranged on the second layer; and

wherein a layer of the first material is deposited over portions of the first layer of the second hardmask prior to forming the alternating blocks of the first material and the second material.

2. The method of claim 1 , wherein the first hardmask is a nitride material.

3. The method of claim 1 , wherein the first layer of the second hardmask includes a nitride material.

4. The method of claim 1 , wherein the second layer of the second hardmask includes an oxide material.

5. The method of claim 1 , wherein the third layer of the second hardmask includes a polymer material.

6. The method of claim 1 , wherein the first material includes a polystyrene material.

7. The method of claim 1 , wherein the second material includes a poly(methyl methacrylate) (PMMA) material.

8. A method for fabricating a semiconductor device, the method comprising:

forming a first hardmask on a semiconductor substrate;

forming a planarizing layer on the first hardmask;

forming a second hardmask on the planarizing layer, the second hardmask including a first layer arranged on the planarizing layer, a second layer arranged on the first layer, and a third layer arranged on the second layer;

removing portions of the third layer and the second layer to expose portions of the first layer of the second hardmask;

forming alternating blocks of a first material and a second material over exposed portions of the first layer of the second hardmask and the third layer of the second hardmask;

removing the blocks of the second material to expose portions of the planarizing layer;

removing exposed portions of the planarizing layer to expose portions of the first hardmask;

removing portions of the first hardmask to expose portions of the semiconductor substrate;

removing exposed portions of the semiconductor substrate to form a first fin and a second fin, wherein the first fin is arranged under a portion of the planarizing layer;

further removing exposed portions of the semiconductor substrate to increase a height of the first fin and the second fin and removing the first hardmask from above the second fin;

further removing exposed portions of the semiconductor substrate to further increase the height of the first fin and substantially remove the second fin; and

forming a gate stack over a channel region of the first fin;

wherein the planarizing layer includes an organic planarizing material.

9. The method of claim 8 , further comprising depositing a layer of the first material over portions of the first layer of the second hardmask prior to forming the alternating blocks of the first material and the second material.

10. The method of claim 8 , wherein the first hardmask is a nitride material.

11. The method of claim 8 , wherein the first layer of the second hardmask includes a nitride material.

12. The method of claim 8 , wherein the second layer of the second hardmask includes an oxide material.

13. The method of claim 8 , wherein the third layer of the second hardmask includes a polymer material.

14. The method of claim 8 , wherein the first material includes a polystyrene material.

15. The method of claim 8 , wherein the second material includes a poly(methyl methacrylate) (PMMA) material.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded May 12, 2021
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 056987/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 20, 2020
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES INC.
Reel/Frame 054636/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 2, 2020
From: GLOBALFOUNDRIES INC.
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 054633/0001 →
SECURITY AGREEMENT Recorded Nov 29, 2018
From: GLOBALFOUNDRIES INC.
To: WILMINGTON TRUST, NATIONAL ASSOCIATION
Reel/Frame 049490/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 10, 2016
From: CHI, CHENG; LIE, FEE LI; LIU, CHI-CHUN
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 038879/0080 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 10, 2016
From: XIE, RUILONG
To: GLOBALFOUNDRIES, INC.
Reel/Frame 038879/0158 →
Continuity (1)
Related Publication 20170358662A1 · Dec 14, 2017