OTPROM for post-process programming using selective breakdown
At least one method, apparatus and system disclosed involves hard-coding data into an integrated circuit device. An integrated circuit device provided. Data for hard-wiring information into a portion of the integrated circuit device is received. A stress voltage signal is provided to a portion of a transistor of the integrated circuit device for causing a dielectric breakdown of the portion of the transistor for hard-wiring the data.
1. An integrated circuit device, comprising:
a transistor, comprising:
a source region on a substrate;
a gate region on said substrate adjacent said source region; and
a drain region on said substrate adjacent said gate region;
and
a programming unit adapted to:
receive data for hard-wiring said data into said transistor;
provide an address signal for addressing at least one of said source, gate, or drain regions for dielectric breakdown;
provide a bias condition for causing said dielectric breakdown of at least one of said source, gate, or drain regions based upon said address signal.
2. The integrated circuit device of claim 1 , wherein said transistor in formed on a programming layer of said integrated circuit device.
3. The integrated circuit device of claim 1 , wherein said transistor is a thin transistor susceptible to breakdown of at least one of said source, gate, or drain regions based upon said address signal.
4. The integrated circuit device of claim 1 , further comprising a hard-wire memory cell comprising a plurality of transistors, wherein at least one of the source, gate, or drain regions of the transistors may be addressed for dielectric breakdown.
5. The integrated circuit device of claim 4 , wherein said memory cell comprises a plurality of wire-select signals for selecting at least one transistor for dielectric breakdown.
6. The integrated circuit device of claim 4 , wherein said memory cell comprises a plurality of transistor pairs, wherein each transistor pair comprises a thick transistor coupled to a thin transistor, wherein at least one of the source, gate, or drain regions of the thin transistor is susceptible to breakdown based upon a write bias condition.
7. The integrated circuit device of claim 6 , wherein at least one of said gate, source, or drain regions is targeted for dielectric breakdown to store at least one of a logic high value as a result of said dielectric breakdown, or a logic low value as a result of not experiencing a dielectric breakdown.
8. The integrated circuit device of claim 7 , further comprising a controller, wherein said controller is adapted to read at least one of said logic high value or said logic low value.
9. The integrated circuit device of claim 4 , wherein said memory cell comprises a plurality of transistor pairs, wherein each transistor pair comprises a thick transistor coupled to a thin transistor, wherein at least one of the source, gate, or drain regions of the thin transistor is susceptible to breakdown based upon a bias condition.
10. An integrated circuit device, comprising:
a first plurality of thick oxide transistors, wherein each thick oxide transistor comprises:
a source region on a substrate;
a gate region on said substrate adjacent said source region; and
a drain region on said substrate adjacent said gate region;
a second plurality of thin oxide transistors, wherein each thin oxide transistor comprises:
a source region on a substrate;
a gate region on said substrate adjacent said source region; and
a drain region on said substrate adjacent said gate region;
and
a programming unit adapted to:
receive data for hard-wiring said data into at least one said thin oxide transistor;
provide an address signal for addressing at least one of said source, gate, or drain regions of said at least one thin oxide transistor for dielectric breakdown;
provide a bias condition for causing said dielectric breakdown of at least one of said source, gate, or drain regions based upon said address signal.
11. The integrated circuit device of claim 10 , wherein said first plurality of thick oxide transistors and said second plurality of thin oxide transistors are formed on a programming layer of said integrated circuit device.
12. The integrated circuit device of claim 10 , wherein said thin oxide transistors are susceptible to breakdown of at least one of said source, gate, or drain regions based upon said address signal; and said thick oxide transistors are immune to breakdown of all of said source, gate, and drain regions upon exposure to said bias condition.
13. The integrated circuit device of claim 10 , wherein said first plurality of thick oxide transistors and said second plurality of thin oxide transistors are components of a hard-wire memory cell.
14. The integrated circuit device of claim 13 , wherein said memory cell comprises a plurality of wire-select signals for selecting at least one thin oxide transistor for dielectric breakdown.
15. The integrated circuit device of claim 13 , wherein a thick transistor of said first plurality is coupled to a thin transistor of said second plurality, wherein at least one of the source, gate, or drain regions of the thin transistor is susceptible to breakdown based upon a write bias condition.
16. The integrated circuit device of claim 15 , wherein at least one of said gate, source, or drain regions is targeted for dielectric breakdown to store at least one of a logic high value as a result of said dielectric breakdown, or a logic low value as a result of not experiencing a dielectric breakdown.
17. The integrated circuit device of claim 16 , further comprising a controller, wherein said controller is adapted to read at least one of said logic high value or said logic low value.
18. An integrated circuit device, comprising:
a first plurality of thick oxide transistors, wherein each thick oxide transistor comprises:
a source region;
a gate region adjacent said source region; and
a drain region adjacent said gate region;
a second plurality of thin oxide transistors, wherein each thin oxide transistor comprises:
a source region;
a gate region adjacent said source region; and
a drain region adjacent said gate region;
a first word line; and
a second word line;
and
a programming unit adapted to:
receive data for hard-wiring said data into at least one said thin oxide transistor;
provide an address signal for addressing at least one of said source, gate, or drain regions of said at least one thin oxide transistor for dielectric breakdown;
provide a first voltage level for causing said dielectric breakdown of at least one of said source, gate, or drain regions based upon said address signal.
19. The integrated circuit device of claim 18 , wherein said first plurality of thick oxide transistors and said second plurality of thin oxide transistors are components of a hard-wire memory cell.
20. The integrated circuit device of claim 19 , wherein said memory cell comprises a plurality of wire-select signals for selecting at least one thin oxide transistor for dielectric breakdown.