OTPROM for post-process programming using selective breakdown

1. A method for hard-coding data into an integrated circuit device, comprising:

providing an integrated circuit device comprising a first plurality of thick oxide transistors, a second plurality of thin oxide transistors, a first word line, and a second word line, wherein a gate of each thin oxide transistor is coupled to a source or a drain of one thick oxide transistor, the first word line is coupled to a source of each thin oxide transistor, the second word line is coupled to a drain of each thin oxide transistor, the thin oxide transistors are susceptible to breakdown at a first voltage level, and the thick oxide transistors are immune to breakdown at the first voltage level;

receiving data for hard-wiring said data into a portion of said integrated circuit device; and

providing a stress voltage signal having the first voltage level to at least one of a source or a drain of at least one thin oxide transistor of said integrated circuit device for causing a dielectric breakdown of said at least one of said source or said drain of said at least one thin oxide transistor for hard-wiring said data.

2. The method of claim 1 , wherein providing said integrated circuit device comprises fabricating said integrated circuit, wherein fabricating comprises fabricating a programming layer comprising a plurality of said thin oxide transistors susceptible to said breakdown of a targeted portion of said thin oxide transistors.

3. The method of claim 1 , wherein receiving data for hard-wiring comprises receiving a program code for hard-coding said program code into said integrated circuit device.

4. The method of claim 1 , wherein providing a stress voltage signal to a portion a transistor of said integrated circuit device for causing a dielectric breakdown of said portion comprises providing an address for targeting a portion of said transistor for dielectric breakdown.

5. The method of claim 4 , wherein providing a stress voltage signal to a portion of a transistor of said integrated circuit device for causing a dielectric breakdown of said portion comprises providing a bias condition such that said portion of said transistor targeted by said address is caused to have a dielectric breakdown.

6. The method of claim 5 , wherein providing said bias condition comprises providing a bias condition such that a least one of a source region and a drain region of the gate oxide of said transistor is targeted by said address is caused to have a dielectric breakdown.

7. The method of claim 5 , wherein providing said bias condition comprises providing arranging a plurality of transistors such that at least one of a gate, source, or drain of at least one of said plurality of transistors is provided with a differential voltage of plus VDD and minus VDD, wherein said address targets at least one of said gate, source, or drain for dielectric breakdown based upon said differential voltage.

8. The method of claim 1 , wherein said at least one of said source or said drain targeted for dielectric breakdown stores at least one of a logic high value as a result of said dielectric breakdown, or a logic low value as a result of not experiencing a dielectric breakdown.

9. The method of claim 8 , further comprising reading at least one of said logic high value or said logic low value.

10. The method of claim 1 , wherein the integrated circuit device comprises four thick oxide transistors and four thin oxide transistors.

11. The method of claim 1 , wherein the source of at least one thin oxide transistor is a gate-to-source capacitor.

12. The method of claim 1 , wherein the drain of at least one thin oxide transistor is a gate-to-drain capacitor.