Multicode receiver
View Patent ↗A code division multiple access (CDMA) receiver detects, de-scrambles, and de-spreads multiple channels that utilize different binary codes. The processing that is common to all channels can be performed once thus saving gate count and power consumption.
1. A code-divisional access (CDMA) receiver for de-scrambling and de-spreading a received signal that was scrambled by a complex scrambling code into a first integrator input and a second integrator input, the received signal having in-phase and quadrature components, wherein the first integrator input and the second integrator input estimate a first and second communication signals that were scrambled by first and second scrambling codes, respectively, the CDMA receiver comprising:
a summer for producing a sum signal by adding the in-phase and quadrature components of the received signal;
a substractor for producing a difference signal by computing the difference between the in-phase component and the quadrature components of the received signal;
a selector for selecting one of the sum and difference signals to be an imaginary component based on the complex scrambling code and for selecting the other one of the sum and difference signals to be a real component;
a first selectable negation circuit for producing the first integrator input by selectively negating the real and imaginary components based on the complex scrambling code and the first scrambling code; and
a second selectable negation circuit for producing the second integrator input by selectively negating the real and imaginary components based on the complex scrambling code and the second scrambling code.
2. The CDMA receiver of claim 1 , wherein the difference signal is equal to the in-phase component minus the quadrature component.
3. The CDMA receiver of claim 2 , wherein the complex scrambling code has a scrambling real component and a scrambling imaginary component, and wherein the sum signal is selected as the imaginary component if a bit of the scrambling real component and a corresponding bit of the scrambling imaginary component of the complex scrambling code are of a different value, and the difference signal is selected as the imaginary component if a bit of the scrambling real component and a corresponding bit of the scrambling imaginary component of the complex scrambling code are of the same value.
4. The CDMA receiver of claim 3 , wherein if the difference signal is selected as the imaginary component, the imaginary component is negated.
5. The CDMA receiver of claim 1 , wherein the difference signal is equal to the quadrature component minus the in-phase component.
6. The CDMA receiver of claim 5 , wherein the complex scrambling code has a scrambling real component and a scrambling imaginary component, and wherein the sum signal is selected as the imaginary component if a bit of the scrambling real component and a corresponding bit of the scrambling imaginary component of the complex scrambling code are of a different value, and the difference signal is selected as the imaginary component if a bit of the scrambling real component and a corresponding bit of the scrambling imaginary component of the complex scrambling code are of the same value.
7. The CDMA receiver of claim 6 , wherein if the sum signal is selected as the imaginary component, the imaginary component is negated.
8. The CDMA receiver of claim 1 , wherein the complex scrambling code has a scrambling real component and a scrambling imaginary component and wherein the real and imaginary components are negated to produce the first integrator input if a bit of the scrambling real component of the complex scrambling code and a corresponding bit of the first scrambling code are of a different value.
9. The CDMA receiver of claim 1 , wherein the complex scrambling code has a scrambling real component and a scrambling imaginary component, and wherein the real and imaginary components are negated to produce the second integrator input if a bit of the scrambling real component of the complex scrambling code and a corresponding bit of the second scrambling code are of a different value.
10. A method of de-spreading a received signal that was scrambled by a complex scrambling code into de-scrambled first and second communication signals, the received signal having in-phase and quadrature components, wherein the de-scrambled first and second communication signals were spread by first and second scrambling codes, respectively, the method comprising:
producing a sum signal by adding the in-phase and quadrature components of the received signal;
producing a difference signal by computing the difference between the in-phase component and the quadrature component of the received signal;
selecting one of the sum and difference signals to be an imaginary component based on the complex scrambling code;
selecting the other one of the sum and difference signals to be a real component;
producing a first integrator input by selectively negating the real and imaginary components based on the complex scrambling code and the first scrambling code; and
producing a second integrator input by selectively negating the real and imaginary components based on the complex scrambling code and the second scrambling code.
11. The method of claim 10 , wherein the difference signal is equal to the in-phase component minus the quadrature component.
12. The method of claim 11 , wherein the complex scrambling code has a scrambling real component and a scrambling imaginary component, and wherein the sum signal is selected as the imaginary component if a bit of the scrambling real component and a corresponding bit of the scrambling imaginary component of the complex scrambling code are of a different value, and the difference signal is selected as the imaginary component if a bit of the scrambling real component and a corresponding bit of the scrambling imaginary component of the complex scrambling code are of the same value.
13. The method of claim 12 , wherein if the difference signal is selected as the imaginary component, the imaginary component is negated.
14. The method of claim 10 , wherein the difference signal is equal to the quadrature component minus the in-phase component.
15. The method of claim 14 , wherein the complex scrambling code has a scrambling real component and a scrambling imaginary component, and wherein the sum signal is selected as the imaginary component if a bit of the scrambling real component and a corresponding bit of the scrambling imaginary component of the complex scrambling code are of a different value, and the difference signal is selected as the imaginary component if a bit of the scrambling real component and a corresponding bit of the scrambling imaginary component of the complex scrambling code are of the same value.
16. The method of claim 15 , wherein if the sum signal is selected as the imaginary component, the imaginary component is negated.
17. The method of claim 10 , wherein the complex scrambling code has a scrambling real component and a scrambling imaginary component, and wherein the real and imaginary components are negated to produce the first integrator input if a bit of the scrambling real component of the complex scrambling code and a corresponding bit of the first scrambling code are of a different value.
18. The method of claim 10 , wherein the complex scrambling code has a scrambling real component and a scrambling imaginary component, and wherein the real and imaginary components are negated to produce the second integrator input if a bit of the scrambling real component of the complex scrambling code and a corresponding bit of the second scrambling code are a different value.