IP Library Granted Patent US 6,981,090
Granted Patent B1
US 6,981,090 · App. 09/893,050 · Granted Dec 27, 2005

Multiple use of microcontroller pad

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Quick Facts
Patent No.
US 6,981,090
App. No.
09/893,050
Granted
Dec 27, 2005
Kind
B1
Abstract

A circuit arrangement permits a microcontroller wirebond pad to be configured to be an analog or digital input or output. The circuit arrangement uses any of a plurality of switching configurations to selectively determine the use of the wirebond pad under control of the microcontroller's processor. The microcontroller can be configured using configurable analog and configurable digital blocks to perform any of a plurality of functions with certain of the pinouts determined under program control.

Claims (23)

1. A microcontroller, comprising:

a circuit comprising an analog circuit and a digital circuit wherein said analog circuit comprises a dedicated analog input and a dedicated analog output and said digital circuit comprises a dedicated digital input and a dedicated digital output;

a wirebond pad;

a processor; and

a user selectable switching circuit that selectively connects at least one of said dedicated analog input, said dedicated analog output, said dedicated digital input and said dedicated digital output to the wirebond pad under control of the processor after packaging of said circuit.

2. The microcontroller according to claim 1 , wherein the analog circuit comprises a configurable analog circuit block.

3. The microcontroller according to claim 1 , wherein the digital circuit comprises a configurable digital circuit block.

4. The microcontroller according to claim 1 , wherein the switching circuit comprises a tristate analog buffer amplifier coupling the dedicated analog output to the wirebond pad, and wherein the dedicated analog output is switched by tristate control of the tristate analog buffer amplifier.

5. The microcontroller according to claim 1 , wherein the switching circuit comprises an analog buffer amplifier in series with an analog switch coupling the dedicated analog output to the wirebond pad, and wherein the dedicated analog output is switched by the analog switch.

6. The microcontroller according to claim 1 , wherein the switching circuit comprises an analog switch coupling the dedicated analog output to the wirebond pad, and wherein the dedicated analog output is switched by the analog switch.

7. The microcontroller according to claim 1 , wherein the switching circuit comprises an analog switch coupling the dedicated analog input to the wirebond pad, and wherein the dedicated analog input is switched by the analog switch.

8. The microcontroller according to claim 1 , wherein the switching circuit comprises a tristate analog buffer amplifier coupling the dedicated analog input to the wirebond pad, and wherein the dedicated analog input is switched by tristate control of the tristate analog buffer amplifier.

9. The microcontroller according to claim 1 , wherein the switching circuit comprises a tristate logic gate coupling the dedicated digital output to the wirebond pad, and wherein the dedicated digital output is switched by tristate control of the tristate logic gate.

10. The microcontroller according to claim 9 , wherein the tristate logic gate comprises an inverter.

11. The microcontroller according to claim 9 , wherein the tristate logic gate comprises a buffer.

12. The microcontroller according to claim 1 , wherein the switching circuit comprises a multiple input logic gate coupling the dedicated digital output to the wirebond pad, and wherein the dedicated digital output is switched by an input to the multiple input logic gate.

13. The microcontroller according to claim 12 , wherein the multiple input logic gate comprises a NAND gate.

14. The microcontroller according to claim 1 , wherein the switching circuit comprises a tristate logic gate coupling the dedicated digital input to the wire bond pad, and wherein the digital input is switched by tristate control of the tristate logic gate.

15. The microcontroller according to claim 14 , wherein the tristate logic gate comprises an inverter.

16. The microcontroller according to claim 14 , wherein the tristate logic gate comprises a buffer.

17. The microcontroller according to claim 1 , wherein the switching circuit comprises a multiple input logic gate coupling the dedicated digital output to the wirebond pad, and wherein the dedicated digital output is switched by an input to the multiple input logic gate.

18. The microcontroller according to claim 17 , wherein the multiple input logic gate comprises a NAND gate.

19. The microcontroller according to claim 1 , wherein the switching circuit comprises an isolation resistor isolating the wirebond pad from one of a digital input, an analog input and analog output.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 16, 2025
From: MONTEREY RESEARCH LLC
To: SOUTHFORK IP HOLDINGS LLC
Reel/Frame 071299/0161 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Oct 28, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MUFG UNION BANK, N.A.
Reel/Frame 050896/0366 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 25, 2019
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 050829/0230 →
PARTIAL RELEASE OF SECURITY INTEREST IN PATENTS Recorded Sep 26, 2019
From: MUFG UNION BANK, N.A., AS COLLATERAL AGENT
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 050500/0112 →