Damascene process for a T-shaped gate electrode

1. A method of manufacturing an integrated circuit having a T-shaped gate conductor, the method comprising the following steps performed in the order below:

providing a gate dielectric layer above a top surface of a substrate;

providing a silicon and nitrogen containing layer above the gate dielectric layer;

providing an oxide layer above the silicon and nitrogen containing layer;

selectively etching the oxide layer to form a first trench in the oxide layer;

selectively etching the silicon and nitrogen containing layer to form a second trench in the silicon and nitrogen containing layer, the second trench being narrower than the first trench and being disposed below the first trench; and

providing a gate conductor material in the first trench and the second trench to form the T-shaped gate conductor.

2. The method of claim 1 , further comprising removing the oxide layer.

3. The method of claim 2 , further comprising:

removing portions of the silicon and nitrogen containing layer, whereby a pair of spacers remain underneath the gate conductor material in the first trench.

4. The method of claim 3 , wherein the gate conductor material is removed by a polishing process.

5. The method of claim 1 , wherein a width of the first trench is at least 250 Å and less than 1600 Å.

6. The method of claim 5 , wherein the width of the second trench is at least 400 Å and less than 2100 Å.

7. The method of claim 1 , wherein the gate dielectric layer is silicon dioxide.

8. A method of manufacturing a T-shaped gate conductor for an integrated circuit, the method comprising:

providing a first layer above a gate dielectric layer, the gate dielectric layer being above a substrate, the first layer including silicon and nitrogen;

providing a second layer above the first layer;

selectively etching a first aperture in the second layer by etching;

selectively etching a second aperture in the first layer utilizing an etching process, wherein the second aperture is narrower than the first aperture;

filling the first aperture and the second aperture with a gate conductor material; and

removing the gate conductor material above the second layer, thereby leaving the T-shaped gate conductor in the first and second aperture, wherein the gate dielectric is provided before the first layer is provided.

9. The method of claim 8 , wherein:

the second layer is an oxide layer.

10. The method of claim 9 , wherein the gate conductor material is doped or undoped polysilicon material.

11. The method of claim 9 , wherein the gate conductor material is silicided.

12. The method of claim 9 , wherein the oxide layer is silicon dioxide.

13. The method of claim 8 , wherein the gate dielectric layer is silicon dioxide.

14. A method of manufacturing an ultra-large scale integrated circuit including a transistor with a T-shaped gate conductor, the method includes steps of:

providing a gate dielectric layer above a substrate;

after providing the gate dielectric layer, providing a first layer above the gate dielectric layer, the first layer including a silicon and nitrogen;

providing an oxide layer over the first layer;

selectively etching a first trench in the oxide layer;

selectively etching a second trench in the first layer, the second trench having a smaller width than the first trench; and

providing a gate conductor material in the first trench and in the second trench to form the T-shaped gate conductor.

15. The method of claim 14 , further comprising removing the oxide layer.

16. The method of claim 14 , further comprising removing portions of the first layer to leave spacers underneath the gate conductor material in the first trench, the removal process utilizing the gate conductor material as a mask.

17. The method of claim 14 , wherein the gate dielectric layer is silicon dioxide.

18. The method of claim 14 , wherein the gate conductor material is doped polysilicon.

19. The method of claim 14 , wherein the first trench is between 1600 Å and 250 Å wide.