Patent Assignment
Reel/Frame 023119/0083
Affirmation of Patent Assignment
Recorded: 2009-08-18
Received: 2009-08-18
Pages: 180
Assignor
ADVANCED MICRO DEVICES, INC.
Executed: 2009-06-30
Assignee
GLOBALFOUNDRIES INC.
P.O. BOX 309, UGLAND HOUSE, GRAND CAYMAN, KYX, KY1-1104, CAYMAN ISLANDS
Covered Properties
(100)
Method for Forming a Self-Aligned Nitrogen-Containing Copper Silicide Capping Layer in a Microstructure Device
Application:
11/853,994 →
Preventative Maintenance Scheduling Incorporating Facility and Loop Optimization
Application:
11/756,710 →
Semiconductor Memory Devices and Methods for Fabricating the Same
Application:
11/692,313 →
Method of Forming an Etch Indicator Layer for Reducing Etch Non-Uniformities
Application:
11/688,280 →
Methods for Fabricating Device Features Having Small Dimensions
Application:
11/669,389 →
Method and System for Determining Utilization of Process Tools in a Manufacturing Environment Based on Characteristics of an Automated Material Handling System
Application:
11/623,619 →
Derived Metric for Monitoring Die Placement
Application:
11/622,635 →
Method and Apparatus for Scheduling Pilot Lots
Application:
11/616,710 →
Method for Reducing Silicide Defects by Removing Contaminants Prior to Drain/Source Activation
Application:
11/567,802 →
Method for Reducing Polish-Induced Damage in a Contact Structure by Forming a Capping Layer
Application:
11/559,652 →
Technique for Forming a Strained Transistor by a Late Amorphization and Disposable Spacers
Application:
11/550,941 →
Method and System for Modeling a Stream of Products in a Manufacturing Environment by Process and Tool Categorization
Application:
11/550,265 →
Method and System for Measurement Data Evaluation in Semiconductor Processing by Correlation-Based Data Filtering
Application:
11/539,917 →
Method and Apparatus for Selecting Sites for Sampling
Application:
11/539,800 →
Method and Apparatus for Implementing a Universal Coordinate System for Metrology Data
Application:
11/539,788 →
Stressed Field Effect Transistor and Methods for Its Fabrication
Application:
11/536,126 →
Metal Cage Structure and Method for Emi Shielding
Application:
11/528,253 →
Method of Forming Doped Regions in the Bulk Substrate of an Soi Substrate to Control the Operational Characteristics of Transistors Formed Thereabove, and an Integrated Circuit Device Comprising Same
Application:
11/533,460 →
Trench Isolation Structure for a Semiconductor Device with Reduced Sidewall Stress and a Method of Manufacturing the Same
Application:
11/532,967 →
Transistor Gate Shape Metrology Using Multiple Data Sources
Application:
11/469,206 →
Embedded Strain Layer in Thin Soi Transistors and a Method of Forming the Same
Application:
11/466,572 →
Controlling an I/O Mmu
Application:
11/503,390 →
Method for Fabricating Stress Enhanced Mos Circuits
Application:
11/464,090 →
Double-Sided Waffle Pack
Application:
11/461,960 →
Cpu Mode-Based Cache Allocation for Image Data
Application:
11/482,454 →
Systems and Methods for Forming Multiple Fin Structures Using Metal-Induced-Crystallization
Application:
11/428,722 →
Etch Stop Layer for a Metallization Layer with Enhanced Etch Selectivity and Hermeticity
Application:
11/426,970 →
Methods of Quantifying Variations Resulting from Manufacturing-Induced Corner Rounding of Various Features, and Structures for Testing Same
Application:
11/425,913 →
Low-Power Multiple-Channel Fully Depleted Quantum Well Cmosfets
Application:
11/445,345 →
Contact Resistance Test Structure and Methods of Using Same
Application:
11/421,217 →
Use of Scanning Theme Implanters and Annealers for Selective Implantation and Annealing
Application:
11/420,819 →
Method and Apparatus for Determining Surface Characteristics by Using Spm Techniques with Acoustic Excitation and Real-Time Digitizing
Application:
11/420,325 →
Method and Semiconductor Structure for Monitoring the Fabrication of Interconnect Structures and Contacts in a Semiconductor Device
Application:
11/419,782 →
Technique for Reducing Silicide Defects by Reducing Deleterious Effects of Particle Bombardment Prior to Silicidation
Application:
11/419,540 →
Method for Increasing Manufacturability of a Circuit Layout
Application:
11/437,312 →
Method and System for Estimating a State of an Uninitialized Advanced Process Controller by Using Segregated Controller Data
Application:
11/383,005 →
Lga Fixture for Indium Assembly Process
Application:
11/381,089 →
Technique for Reducing Etch Damage During the Formation of Vias and Trenches in Interlayer Dielectrics
Application:
11/380,094 →
Method for Fabricating a Semiconductor Component Including a High Capacitance Per Unit Area Capacitor
Application:
11/409,362 →
Integrated Circuit Design with Cell-Based Macros
Application:
11/397,550 →
Method and Apparatus for Tracking Reticle History
Application:
11/278,589 →
System and Method for Inspecting a Semiconductor Sample
Application:
11/386,623 →
Method and Apparatus for Identifying Outlier Data
Application:
11/371,771 →
System for Phase Tracking and Equalization Across a Byte Group for Asymmetric Control of High-Speed Bidirectional Signaling
Application:
11/368,792 →
Determining Metrology Sampling Decisions Based on Fabrication Simulation
Application:
11/363,748 →
Circuit Lid with a Thermocouple
Application:
11/362,749 →
Semiconductor on Insulator Substrate and Devices Formed Therefrom
Application:
11/361,207 →
Method and Apparatus for Adjusting Processing Speeds Based on Work-in-Process Levels
Application:
11/342,757 →
Thermally Conductive Integrated Circuit Mounting Structures
Application:
11/338,033 →
Selectable Open Circuit and Anti-Fuse Element
Application:
11/306,663 →
System and Method for Operating Components of an Integrated Circuit at Independent Frequencies and/or Voltages
Application:
11/325,054 →
Semiconductor Device Having Nanowire Contact Structures and Method for Its Fabrication
Application:
11/323,290 →
Secure Patch Installation for Wwan Systems
Application:
11/316,499 →
Memory Access Request Arbitration
Application:
11/297,856 →
Scanner Optimization for Reduced Across-Chip Performance Variation Through Non-Contact Electrical Metrology
Application:
11/298,340 →
Technique for Forming Interconnect Structures with Reduced Electro and Stress Migration and/or Resistivity
Application:
11/292,537 →
Thin Film Germanium Diode with Low Reverse Breakdown
Application:
11/290,787 →
Technique for Enhancing Thermal and Mechanical Characteristics of an Underfill Material of a Substrate/Die Assembly
Application:
11/284,292 →
Technique for Cd Measurement on the Basis of Area Fraction Determination
Application:
11/281,169 →
Isolation Region Bird's Beak Suppression
Application:
11/258,209 →
Bit Line Implant
Application:
11/254,769 →
Use of Ta-Capped Metal Line to Improve Formation of Memory Element Films
Application:
11/251,291 →
Method of Reworking a Semiconductor Structure
Application:
11/247,369 →
Hierarchical Mru Policy for Data Cache
Application:
11/242,578 →
Method and Apparatus for Selecting Wafers for Sampling
Application:
11/239,814 →
Methods for Fabrication of a Stressed Mos Device
Application:
11/235,791 →
Stressed Mos Device and Methods for Its Fabrication
Application:
11/231,405 →
Data Representation Relating to a Non-Sampled Workpiece
Application:
11/224,388 →
Method and Apparatus for Determining a Root Cause of a Statistical Process Control Failure
Application:
11/220,436 →
Method of Process Control
Application:
11/214,115 →
Method of Forming a Semiconductor Device
Application:
11/209,871 →
Sonos Memory Cell Having High-K Dielectric
Application:
11/196,434 →
Method of Forming Contact Pads
Application:
11/196,024 →
Automated Control Thread Determination Based Upon Post-Process Consideration
Application:
11/192,691 →
Using a Shuffle Unit to Implement Shift Operations in a Processor
Application:
11/192,153 →
Semiconductor Substrate Layer Configured for Inducement of Compressive or Expansive Force
Application:
11/179,282 →
Burn-In Using System-Level Test Hardware
Application:
11/174,823 →
Self-Aligned Dual Stressed Layers for Nfet and Pfet
Application:
11/160,676 →
Sram Devices Utilizing Tensile-Stressed Strain Films and Methods for Fabricating the Same
Application:
11/174,400 →
Use of Supercritical Fluid to Dry Wafer and Clean Lens in Immersion Lithography
Application:
11/173,257 →
Method of Forming a Memory Device Having Improved Erase Speed
Application:
11/165,330 →
Pci-X Error Correcting Code (Ecc) Pin Sharing Configuration
Application:
11/151,317 →
Automated Integrated Circuit Device Manufacturing Facility Using Distributed Control
Application:
11/148,092 →
Microprocessor Including a Configurable Translation Lookaside Buffer
Application:
11/146,863 →
Serial Interface Having a Read Temperature Command
Application:
11/140,803 →
Chip Bond Layout for Chip Carrier for Flip Chip Applications
Application:
11/135,720 →
Semiconductor Devices and Methods for Forming the Same
Application:
11/135,711 →
System for providing collaborative communications environment for manufacturers and potential customers
Application:
11/135,591 →
Method and Apparatus for Fast Disturbance Detection and Classificiation
Application:
11/130,459 →
Polymer Spacers for Creating Sub-Lithographic Spaces
Application:
11/127,175 →
System and Method for Trace Messaging
Application:
11/125,456 →
Silicon Nitride Etching Methods
Application:
10/908,252 →
Method for Manufacturing a Memory Device Having a Nanocrystal Charge Storage Region
Application:
11/116,538 →
Method for Manufacturing a Memory Device Having a Nanocrystal Charge Storage Region
Application:
11/116,551 →
Radical Oxidation for Bitline Oxide of Sonos
Application:
11/113,507 →
Method for Forming Memory Array Bitlines Comprising Epitaxially Grown Silicon and Related Structure
Application:
11/112,607 →
Biased, Triple-Well Fully Depleted Soi Structure
Application:
11/111,409 →
Method for Manufacturing a Semiconductor Component That Inhibits Formation of Wormholes
Application:
11/109,964 →
A System for Controlling Power to Sequential and Combinatorial Logic Circuitry in an Integrated Circuit
Application:
11/105,814 →
Method for Reducing Edge Array Erosion in a High-Density Array
Application:
11/101,285 →