Granted Patent B1

US 7,465,644 · App. 11/258,209 · Granted Dec 16, 2008

Abstract

Claims (50)

1. A method, comprising:

forming a first layer of oxide over a semiconducting layer;

forming a layer of nitride over the first layer;

forming a second layer of oxide over the nitride layer;

forming a layer of Al 2 O 3 , HfO 2 or Ta 2 O 5 over the second layer of oxide;

etching a pattern in the layer of Al 2 O 3 , HfO 2 or Ta 2 O 5 to expose portions of the semiconducting layer; and

oxidizing at least one of the exposed portions of the semiconducting layer, using an oxidation process, to form an electrical isolation region, where the oxidation process directly oxidizes the at least one of the exposed portions of the semiconducting layer without oxidizing through any other intervening layers.

2. The method of claim 1 , wherein the layer of Al 2 O 3 , HfO 2 or Ta 2 O 5 has a thickness ranging from about 40 Å to about 150 Å.

3. The method of claim 1 , wherein the isolation region has a thickness ranging from about 200 Å to about 1500 Å.

4. The method of claim 1 , wherein the semiconducting layer comprises silicon and wherein the isolation region comprises a silicon oxide.

5. The method of claim 1 , wherein the semiconducting layer comprises silicon and where the oxidation process comprises:

a local oxidation of silicon (LOCOS) process.

6. The method of claim 1 , wherein the isolation region does not substantially encroach a region beneath the layer of Al 2 O 3 , HfO 2 or Ta 2 O 5 .

7. The method of claim 1 , wherein the isolation region does not substantially deform the layer of Al 2 O 3 , HfO 2 or Ta 2 O 5 .

8. A structure for electrically isolating semiconductor devices, comprising:

a semiconducting layer;

a first layer of oxide formed directly on the semiconducting layer;

a layer of nitride formed directly on the first layer;

a second layer of oxide formed directly on the nitride layer;

a layer of Al 2 O 3 , HfO 2 or Ta 2 O 5 formed in a pattern directly on the second layer, where the pattern exposes a portion of the semiconducting layer; and

an electrical isolation region formed in the exposed portion of the semiconducting layer, wherein the isolation region does not substantially encroach a region beneath the layer of Al 2 O 3 , HfO 2 or Ta 2 O 5 .

9. The structure of claim 8 , wherein the isolation region has a thickness ranging from about 200 Å to about 1500 Å.

10. The structure of claim 8 , wherein the layer of Al 2 O 3 , HfO 2 or Ta 2 O 5 is not deformed by formation of the electrical isolation region.

11. The structure of claim 8 , wherein a thickness of the layer of Al 2 O 3 , HfO 2 or Ta 2 O 5 ranges from about 40 Å to about 150 Å.

12. The structure of claim 8 , wherein the semiconducting layer comprises silicon and wherein the isolation region comprises a silicon oxide.

13. The structure of claim 8 , wherein the semiconducting layer comprises silicon and wherein the isolation region is formed using a local oxidation of silicon (LOCOS) technique.

14. A method of forming an electrical isolation region in a semiconductor substrate, comprising:

forming a first layer of oxide over the semiconductor substrate;

forming a layer of nitride over the first layer;

forming a second layer of oxide over the nitride layer;

forming a layer of HfO 2 or Ta 2 O 5 over the second layer of oxide in a pattern, wherein the pattern exposes a portion of the semiconductor substrate; and

locally oxidizing the exposed portion of the semiconductor substrate to form an electrical isolation region, wherein the isolation region does not substantially encroach an area beneath the layer of HfO 2 or Ta 2 O 5 .

15. The method of claim 14 , wherein a thickness of the layer of HfO 2 or Ta 2 O 5 ranges from about 40 Å to about 150 Å.

16. The method of claim 14 , wherein the isolation region comprises a silicon oxide.

17. The method of claim 14 , wherein the isolation region has a thickness ranging from about 200 Å to about 1500 Å.

18. A method, comprising:

forming a first layer of oxide directly on a layer of semiconducting material;

forming a layer of nitride directly on the first layer;

forming a second layer of oxide directly on the nitride layer;

forming a layer comprising one of Al 2 O 3 , HfO 2 or Ta 2 O 5 directly on the second layer of oxide;

etching a pattern in the first layer of oxide, the nitride layer, the second layer of oxide and the layer comprising one of Al 2 O 3 , HfO 2 or Ta 2 O 5 to expose one or more portions of the layer of semiconducting material; and

oxidizing at least one of one or more exposed portions of the layer of semiconducting material to form an electrical isolation region.

19. The method of claim 18 , where forming the layer comprising one of Al 2 O 3 , HfO 2 or Ta 2 O 5 comprises:

forming the layer comprising one of Al 2 O 3 , HfO 2 or Ta 2 O 5 directly on the second layer of oxide to a thickness ranging from about 40 Å to about 150 Å.

20. The method of claim 18 , where the electrical isolation region has a thickness ranging from about 200 Å to about 1500 Å.

21. The method of claim 18 , where the semiconducting material comprises silicon and wherein the isolation region comprises a silicon oxide.

22. The method of claim 18 , where the semiconducting material comprises silicon and wherein the oxidizing comprises:

using a local oxidation of silicon (LOCOS) technique.

23. The method of claim 18 , where the electrical isolation region does not substantially encroach a region beneath the first layer of oxide, the nitride layer, the second layer of oxide and the layer comprising one of Al 2 O 3 , HfO 2 or Ta 2 O 5 .

24. The method of claim 18 , where the electrical isolation region does not substantially deform the first layer of oxide, the nitride layer, the second layer of oxide and the layer comprising one of Al 2 O 3 , HfO 2 or Ta 2 O 5 .

Assignments (8)