Semiconductor on insulator substrate and devices formed therefrom
View Patent ↗A semiconductor on insulator (SOI) device is comprised of a layer of a dielectric material having a perovskite lattice, such as a rare earth scandate. The dielectric material is selected to have an effective lattice constant that enables growth of semiconductor material having a diamond lattice directly on the dielectric. Examples of the rare earth scandate dielectric include gadolinium scandate (GdScO 3 ), dysprosium scandate (DyScO 3 ), and alloys of gadolinium and dysprosium scandate (Gd 1−x Dy x ScO 3 ).
1. A semiconductor on insulator (SOI) device comprising:
a substrate comprising a layer of gadolinium scandate (GdScO 3 ) dielectric material;
a region of a first semiconductor material formed on the gadolinium scandate (GdScO 3 ) layer; and
a first MOSFET having a channel comprising at least a portion of the region of the first semiconductor material.
2. The device claimed in claim 1 , wherein the first semiconductor material is a single crystal semiconductor material having a diamond lattice.
3. The device claimed in claim 1 , wherein the first semiconductor material is formed on a (001) face of the gadolinium scandate (GdScO 3 ) lattice.
4. The device claimed in claim 1 , wherein the first semiconductor material is silicon.
5. The device claimed in claim 4 , wherein the gadolinium scandate (GdScO 3 ) lattice imparts a tensile strain to the silicon.
6. The device claimed in claim 1 , wherein the first semiconductor material is silicon germanium.
7. The device claimed in claim 6 , wherein the gadolinium scandate (GdScO 3 ) lattice imparts a tensile strain to the silicon germanium.
8. The device claimed in claim 6 , wherein the gadolinium scandate (GdScO 3 ) lattice imparts a compressive strain to the silicon germanium.
9. The device claimed in claim 1 , wherein the first semiconductor material is germanium.
10. The device claimed in claim 1 , wherein the first semiconductor material is a compound semiconductor material.
11. The device claimed in claim 1 , wherein the MOSFET comprises:
a gate insulator formed over the region of the first semiconductor material;
a gate formed on the gate insulator;
a spacer formed around the gate; and
source and drain regions at opposing sides of the gate.
12. The device claimed in claim 1 , further comprising:
a region of a second semiconductor material formed on the gadolinium scandate (GdScO 3 ) layer; and
a second MOSFET having a channel comprising at least a portion of the region of the second semiconductor material,
wherein the gadolinium scandate (GdScO 3 ) layer imparts a tensile strain to the first semiconductor material, and
wherein the gadolinium scandate (GdScO 3 ) layer imparts a compressive strain to the second semiconductor material.
13. The device claimed in claim 12 , wherein the first semiconductor material is a silicon germanium alloy having a lattice constant that is less than an effective lattice constant of the gadolinium scandate (GdScO 3 ) material, and
wherein the second semiconductor material is a silicon germanium alloy having a lattice constant that is greater than the effective lattice constant of the gadolinium scandate (GdScO 3 ) dielectric material.
14. The device claimed in claim 12 , wherein the first MOSFET and the second MOSFET are connected to form a CMOS device.
15. A semiconductor on insulator (SOI) device comprising:
a substrate comprising a layer of dysprosium scandate (DyScO 3 ) dielectric material;
a region of a first semiconductor material formed on the dysprosium scandate (DyScO 3 ) layer; and
a first MOSFET having a channel comprising at least a portion of the region of the first semiconductor material.
16. The device claimed in claim 15 , wherein the first semiconductor material is a single crystal semiconductor material having a diamond lattice.
17. The device claimed in claim 15 , wherein the first semiconductor material is formed on a (001) face of the dysprosium scandate (DyScO 3 ) lattice.
18. The device claimed in claim 15 , wherein the first semiconductor material is silicon.
19. The device claimed in claim 18 , wherein the dysprosium scandate (DyScO 3 ) lattice imparts a tensile strain to the silicon.
20. The device claimed in claim 15 , wherein the first semiconductor material is silicon germanium.
21. The device claimed in claim 20 , wherein the dysprosium scandate (DyScO 3 ) lattice imparts a tensile strain to the silicon germanium.
22. The device claimed in claim 20 , wherein the dysprosium scandate (DyScO 3 ) lattice imparts a compressive strain to the silicon germanium.
23. The device claimed in claim 15 , wherein the first semiconductor material is germanium.
24. The device claimed in claim 15 , wherein the first semiconductor material is a compound semiconductor material.
25. The device claimed in claim 15 , wherein the MOSFET comprises:
a gate insulator formed over the region of the first semiconductor material;
a gate formed on the gate insulator;
a spacer formed around the gate; and
source and drain regions at opposing sides of the gate.
26. The device claimed in claim 15 , further comprising:
a region of a second semiconductor material formed on the dysprosium scandate (DyScO 3 ) layer; and
a second MOSFET having a channel comprising at least a portion of the region of the second semiconductor material,
wherein the dysprosium scandate (DyScO 3 ) layer imparts a tensile strain to the first semiconductor material, and
wherein the dysprosium scandate (DyScO 3 ) layer imparts a compressive strain to the second semiconductor material.
27. The device claimed in claim 26 , wherein the first semiconductor material is a silicon germanium alloy having a lattice constant that is less than an effective lattice constant of the dysprosium scandate (DyScO 3 ) material, and
wherein the second semiconductor material is a silicon germanium alloy having a lattice constant that is greater than the effective lattice constant of the dysprosium scandate (DyScO 3 ) material.
28. The device claimed in claim 26 , wherein the first MOSFET and the second MOSFET are connected to form a CMOS device.
29. A semiconductor on insulator (SOI) device comprising:
a substrate comprising a layer of a dielectric material, wherein the dielectric material comprises an alloy of gadolinium and dysprosium scandate (Gd (1−x) Dy x ScO3);
a layer of a first semiconductor material formed on the layer of the dielectric material; and
a first MOSFET having a channel comprising at least a portion of the region of the first semiconductor material.
30. The device claimed in claim 29 , wherein the first semiconductor material is a single crystal semiconductor material having a diamond lattice.
31. The device claimed in claim 29 , wherein the first semiconductor material is formed on a (001) face of the lattice of the alloy of gadolinium and dysprosium scandate (Gd (1−x) Dy x ScO3).
32. The device claimed in claim 29 , wherein the first semiconductor material is silicon.
33. The device claimed in claim 32 , wherein the lattice of the alloy of gadolinium and dysprosium scandate (Gd (1−x) Dy x ScO3) imparts a tensile strain to the silicon.
34. The device claimed in claim 29 , wherein the first semiconductor material is silicon germanium.
35. The device claimed in claim 34 , wherein the lattice of the alloy of gadolinium and dysprosium scandate (Gd (1−x) Dy x ScO3) imparts a tensile strain to the silicon germanium.
36. The device claimed in claim 34 , wherein the lattice of the alloy of gadolinium and dysprosium scandate (Gd (1−x) Dy x ScO3) imparts a compressive strain to the silicon germanium.
37. The device claimed in claim 29 , wherein the first semiconductor material is germanium.
38. The device claimed in claim 29 , wherein the first semiconductor material is a compound semiconductor material.
39. The device claimed in claim 29 , wherein the effective lattice constant of the alloy of gadolinium and dysprosium scandate (Gd (1−x) Dy x ScO3) is in the range of 5.431 Å to 5.657 Å.
40. The device claimed in claim 29 , wherein the MOSFET comprises:
a gate insulator formed over the region of the first semiconductor material;
a gate formed on the gate insulator;
a spacer formed around the gate; and
source and drain regions at opposing sides of the gate.
41. The device claimed in claim 29 , further comprising:
a region of a second semiconductor material formed on the layer of the dielectric material; and
a second MOSFET having a channel comprising at least a portion of the region of the second semiconductor material,
wherein the lattice of the alloy of gadolinium and dysprosium scandate (Gd (1−x) Dy x ScO3) imparts a tensile strain to the first semiconductor material, and,
wherein the lattice of the alloy of gadolinium and dysprosium scandate (Gd (1−x) Dy x ScO3) imparts a compressive strain to the second semiconductor material.
42. The device claimed in claim 41 , wherein the first semiconductor material is a silicon germanium alloy having a lattice constant that is less than an effective lattice constant of the alloy of gadolinium and dysprosium scandate (Gd (1−x) Dy x ScO3), and
wherein the second semiconductor material is a silicon germanium alloy having a lattice constant that is greater than the effective lattice constant of the alloy of gadolinium and dysprosium scandate (Gd (1−x) Dy x ScO3).
43. The device claimed in claim 26 , wherein the first MOSFET and the second MOSFET are connected to form a CMOS device.