Radical oxidation for bitline oxide of SONOS
View Patent ↗Methods are disclosed for fabricating multi-bit SONOS flash memory cells, comprising forming a first dielectric layer and a charge trapping layer over a substrate of a wafer and selectively etching the dielectric and charge trapping layers down to a substrate region to form a bitline opening, then implanting a dopant ion species into the substrate associated with the bitline opening in a bitline region. A radical oxidation process is then used to form a second dielectric layer of a triple layer dielectric-charge trapping-dielectric stack over the charge trapping layer and to fill the bitline opening in the bitline regions of the wafer. Finally, a wordline structure is then formed over the triple layer dielectric-charge trapping-dielectric stack and the bitline regions of the wafer. A multi-bit flash memory array is also disclosed, comprising a bitline region in a substrate, a first dielectric layer overlying the substrate substantially adjacent to and substantially exposing the bitline region, a charge trapping layer overlying the first dielectric layer substantially adjacent to and substantially exposing the bitline region, a bitline oxide isolation structure or layer extending continuously over the bitline region and charge trapping layer, the isolation structure comprising a single dielectric material layer formed by the radical oxidation process, and a conductive wordline overlying the bitline oxide isolation structure or layer.
1. A method of fabricating a flash memory cell in a wafer, comprising:
forming a first dielectric layer and a charge trapping layer of a triple layer dielectric-charge trapping-dielectric stack over a substrate;
selectively etching the dielectric and charge trapping layers down to the substrate to form a bitline opening in a bitline region;
implanting a dopant ion species into the substrate associated with the bitline opening to form a bitline;
performing a radical oxidation process after forming the bitline to form a second dielectric layer of the triple layer dielectric-charge trapping-dielectric stack over the charge trapping layer and filling the bitline opening; and
forming a wordline structure over the second dielectric layer, thereby covering the triple layer dielectric-charge trapping-dielectric stack and the bitline region.
2. The method of claim 1 , further comprising removing a photoresist mask and cleaning the wafer before implanting the dopant ion species into the substrate associated with the bitline opening in the bitline region.
3. The method of claim 1 , wherein the triple layer dielectric-charge trapping-dielectric stack comprises a first dielectric layer overlying the substrate, a nitride layer overlying the first dielectric layer, and a second dielectric layer overlying the nitride layer.
4. The method of claim 1 , wherein the first dielectric layer of the triple layer dielectric-charge trapping-dielectric stack comprises a first dielectric layer overlying the substrate, and the second dielectric layer of the triple layer dielectric-charge trapping-dielectric stack comprises a second dielectric layer overlying the nitride layer and the bitline opening.
5. The method of claim 1 , wherein the wordline structure formed over the triple layer dielectric-charge trapping-dielectric stack and the bitline regions of the wafer comprises a polysilicon material layer.
6. The method of claim 1 , wherein the bitline regions is formed by diffusion of an n+ dopant within the substrate.
7. The method of claim 1 , wherein the radical oxidation process comprises a decoupled plasma oxidation utilizing a partial pressure of ozone or a radical oxygen species of about 0.1% to about 10% and preferably a partial pressure of ozone of about 1.0% to about 5.0%.
8. The method of claim 1 , wherein the radical oxidation processing temperature is performed at about 300° C. to about 600° C. and preferably at a temperature of about 300° C. to about 600° C.
9. The method of claim 1 , wherein the radical oxidation processing time comprises about 1 minute to about 5 minutes.
10. The method of claim 1 , wherein the radical oxidation process takes place in a partial pressure of ozone or a radical oxygen species of about 0.1% to about 10% and preferably a partial pressure of about 1.0% to about 5.0% at a temperature of about 300° C. to about 600° C. and preferably at a temperature of about 300° C. to about 600° C. for a period of about 1 minute to about 5 minutes.
11. The method of claim 1 , wherein forming the triple layer dielectric-charge trapping-dielectric stack comprises:
forming a first dielectric layer over the substrate;
forming a nitride layer over the first dielectric layer; and
forming a second dielectric layer over the nitride layer and within the bitline opening before forming the wordline structure.
12. The method of claim 1 , wherein the triple layer dielectric-charge trapping-dielectric stack comprises an ONO layer.
13. A method of fabricating a multi-bit SONOS flash memory cell, comprising:
forming a first dielectric layer and a charge trapping layer over a substrate of a wafer;
selectively etching the dielectric and charge trapping layers down to a substrate region to form a bitline opening;
implanting a dopant ion species into the substrate associated with the bitline opening thereby forming a bitline region; and
performing a radical oxidation process after forming the bitline to form a second dielectric layer of a triple layer dielectric-charge trapping-dielectric stack over the charge trapping layer and filling the bitline opening over the bitline.
14. The method of claim 13 , further comprising forming a wordline structure over the triple layer dielectric-charge trapping-dielectric stack and the bitline regions of the wafer after the performing the radical oxidation process.