Embedded strain layer in thin SOI transistors and a method of forming the same
View Patent ↗By forming a deep recess through the buried insulating layer and re-growing a strained semiconductor material, an enhanced strain generation mechanism may be provided in SOI-like transistors. Consequently, the strain may also be efficiently created by the embedded strained semiconductor material across the entire active layer, thereby significantly enhancing the performance of transistor devices, in which two channel regions may be defined.
1. A method, comprising:
forming a recess adjacent to a first gate electrode of a first transistor, said first gate electrode formed above a substrate comprising a first crystalline semiconductor layer, a buried insulating layer formed on said first crystalline semiconductor layer and a second crystalline semiconductor layer formed on said buried insulating layer, said recess extending into said first crystalline semiconductor layer;
epitaxially growing a strained semiconductor material in said recess;
forming a drain and source region in said strained semiconductor material by implanting a dopant species into said strained semiconductor material; and
adjusting a dopant profile of said implanted species to define a first channel region and a second channel region, said first channel located at an interface of a gate insulation layer and said second semiconductor layer, said second channel region located at an interface of said buried insulating layer and said second semiconductor layer.
2. The method of claim 1 , further comprising forming a sidewall spacer on sidewalls of said recess.
3. The method of claim 2 , wherein epitaxially growing said strained semiconductor material comprises growing a first portion of said strained semiconductor material, removing an exposed portion of said sidewall spacer in said recess and continuing said epitaxial growth process.
4. The method of claim 1 , further comprising covering a second transistor area while forming said recess and epitaxially growing said strained semiconductor material.
5. The method of claim 4 , further comprising forming a second transistor in said second transistor area, said second transistor including a drain and source region defined in second crystalline semiconductor layer without extending through said buried insulating layer.
6. The method of claim 5 , wherein a conductivity type of said first transistor differs from a conductivity type of said second transistor.
7. The method of claim 5 , wherein said first crystalline semiconductor layer differs from said second crystalline semiconductor layer in at least one of crystalline orientation and material composition.
8. The method of claim 7 , wherein said first transistor is an N-channel transistor and said second semiconductor layer has a <100> orientation.
9. The method of claim 7 , wherein said first transistor is a P-channel transistor and said second semiconductor layer has a <110> orientation.
10. The method of claim 7 , wherein said first transistor is an N-channel transistor and said second semiconductor layer has a <100> orientation and wherein said second transistor is a P-channel transistor and said first semiconductor layer has a <110> orientation.
11. The method of claim 7 , wherein said first transistor is a P-channel transistor and said second semiconductor layer has a <110> orientation and wherein said second transistor is an N-channel transistor and said first semiconductor layer has a <100> orientation.
12. The method of claim 1 , wherein said first crystalline semiconductor layer differs from said second crystalline semiconductor layer in at least one of crystalline orientation and material composition.
13. The method of claim 1 , wherein said strained semiconductor material is selected to generate compressive strain in said second crystalline semiconductor layer.
14. The method of claim 13 , wherein said strained semiconductor material comprises silicon/germanium.
15. The method of claim 14 , wherein said first crystalline semiconductor layer comprises silicon with a <110> orientation.
16. The method of claim 1 , wherein said strained semiconductor material is selected to generate tensile strain in said second crystalline semiconductor layer.
17. The method of claim 16 , wherein said first crystalline semiconductor layer comprises silicon with a <100> orientation.
18. The method of claim 1 , wherein said drain and source regions are raised drain and source regions.