Method for fabricating a semiconductor component including a high capacitance per unit area capacitor
View Patent ↗A method is provided for fabricating a semiconductor component that includes a capacitor having a high capacitance per unit area. The component is formed in and on a semiconductor on insulator (SOI) substrate having a first semiconductor layer, a layer of insulator on the first semiconductor layer, and a second semiconductor layer overlying the layer of insulator. The method comprises forming a first capacitor electrode in the first semiconductor layer and depositing a dielectric layer comprising Ba 1-x Ca x Ti 1-y Zr y O 3 overlying the first capacitor electrode. A conductive material is deposited and patterned to form a second capacitor electrode overlying the dielectric layer, thus forming a capacitor having a high dielectric constant dielectric. An MOS transistor in then formed in a portion of the second semiconductor layer, the MOS transistor, and especially the gate dielectric of the MOS transistor, formed independently of forming the capacitor and electrically isolated from the capacitor.
1. A method for fabricating a semiconductor component including a semiconductor on insulator (SOI) substrate having a first semiconductor layer, a layer of insulator on the first semiconductor layer, and a second semiconductor layer overlying the layer of insulator, the method comprising the steps of:
etching an opening through the layer of insulator to expose a portion of the first semiconductor layer;
depositing a first layer of metal overlying the second semiconductor layer and into the opening and contacting the exposed portion of the first semiconductor layer;
depositing a dielectric layer comprising Ba 1-x Ca x Ti 1-y Zr y O 3 overlying the first layer of metal;
depositing a second layer of metal overlying the dielectric layer;
annealing the dielectric layer at a temperature in excess of 450° C.;
removing a portion of the first layer of metal, the dielectric layer, and the second layer of metal overlying the second semiconductor layer to expose a surface of the second semiconductor layer;
forming a layer of gate insulator at the surface of the second semiconductor layer; and
depositing and patterning a layer of gate electrode material to form a gate electrode overlying the layer of gate insulator.
2. The method of claim 1 wherein the step of depositing a first layer of metal comprises the step of depositing a layer of nickel and the step of depositing a second layer of metal comprises the step of depositing a layer of nickel.
3. The method of claim 1 wherein the step of depositing a dielectric layer comprises the step of depositing a dielectric layer comprising Ba 0.96 Ca 0.04 Ti 0.84 Zr 0.16 O 3 .
4. The method of claim 3 wherein the step of depositing a dielectric layer comprises the step of depositing a dielectric layer by a process of rf magnetron sputtering.
5. The method of claim 1 wherein the step of depositing a dielectric layer comprises the step of depositing a dielectric layer by a process of magnetron sputtering.
6. The method of claim 5 wherein the step of depositing a dielectric layer by a process of magnetron sputtering comprises the step of depositing a dielectric layer by a process of magnetron sputtering using a target comprising barium, calcium, titanium, zirconium, oxygen, and a dopant material.
7. The method of claim 1 wherein the step of annealing the dielectric layer comprises the step of annealing the dielectric layer at a temperature greater than 1000° C.
8. The method of claim 1 further comprising the step of implanting conductivity determining ions through the opening and into the first semiconductor layer to form a first electrode of a capacitor.
9. The method of claim 8 further comprising the steps of:
etching a second opening through at least a portion of the first metal layer to expose a portion of the first electrode; and
depositing a conductive material into the second opening to electrically contact the first metal layer and the first electrode.
10. A method for fabricating a semiconductor component including a semiconductor on insulator (SOI) substrate having a first semiconductor layer, a layer of insulator on the first semiconductor layer, and a second semiconductor layer overlying the layer of insulator, the method comprising the steps of:
etching a first opening extending through the second semiconductor layer to the layer of insulator;
depositing an oxide overlying the second semiconductor layer and filling the first opening;
planarizing the oxide by a process of chemical mechanical planarization to expose a surface of the second semiconductor layer;
etching a second opening extending through the oxide and the layer of insulator to expose a portion of the first semiconductor layer;
implanting conductivity determining ions through the second opening to form an impurity doped region in the first semiconductor layer;
contacting the impurity doped region with a first layer of metal;
depositing a dielectric layer comprising Ba 1-x Ca x Ti 1-y Zr y O 3 over the first layer of metal;
depositing a second layer of metal overlying the dielectric layer;
removing a portion of the first layer of metal, the dielectric layer, and the second layer of metal overlying the second semiconductor layer by a process of chemical mechanical planarization;
etching a third opening through the first layer of metal to expose a portion of the impurity doped region; and
forming a first electrically conductive contact to the impurity doped region and a second electrically conductive contact to the second layer of metal.
11. The method of claim 10 wherein the step of depositing a dielectric layer comprises the step of depositing a dielectric layer comprising Ba 0.96 Ca 0.04 Ti 0.84 Zr 0.16 O 3 .
12. The method of claim 11 wherein the step of depositing a dielectric layer further comprises the step of doping the layer comprising Ba 0.96 Ca 0.04 Ti 0.84 Zr 0.16 O 3 with a dopant material.
13. The method of claim 12 wherein the step of doping comprises the step of doping with a material comprising scandium.
14. The method of claim 10 further comprising the step of annealing the dielectric layer at a temperature above 1000° C.
15. The method of claim 10 further comprising the step of forming an MOS transistor in and on the second semiconductor layer.
16. The method of claim 10 wherein the step of forming a first electrically conductive contact to the impurity doped region further comprises the step of forming the first electrically conductive contact to the first layer of metal.
17. A method for fabricating a semiconductor component including a semiconductor on insulator (SOI) substrate having a first semiconductor layer, a layer of insulator on the first semiconductor layer, and a second semiconductor layer overlying the layer of insulator, the method comprising the steps of:
forming an impurity doped region in the first semiconductor layer;
depositing a first metal layer in electrical contact with the impurity doped region to form a first capacitor electrode;
depositing a dielectric layer comprising Ba 1-x Ca x Ti 1-y Zr y O 3 overlying the first capacitor electrode;
depositing and patterning a metal material to form a second capacitor electrode overlying the dielectric layer;
forming an MOS transistor in a portion of the second semiconductor layer; and
electrically isolating the MOS transistor from the second capacitor electrode by a shallow trench isolation region.
18. The method of claim 17 wherein the step of depositing a dielectric layer comprises the step of depositing a dielectric layer comprising Ba 0.96 Ca 0.04 Ti 0.84 Zr 0.16 O 3 .
19. The method of claim 18 wherein the step of depositing a dielectric layer further comprises the step of doping the dielectric layer.
20. The method of claim 17 further comprising the step of depositing an additional conductive material in contact with the first capacitor electrode.