Technique for reducing etch damage during the formation of vias and trenches in interlayer dielectrics
View Patent ↗By performing a first common etch process for forming a via opening and a delineation trench or open area in a metallization layer with different removal rates, the etch front in the delineation trench or open area may be delayed, thereby significantly reducing the probability of wafer arcing. Subsequently, the delineation trench or open area may be etched down to the respective etch stop layer in a further common etch process, during which a trench is formed above the via opening.
1. A method, comprising:
forming a via opening and a delineation area in a dielectric layer of a metallization layer in a first common etch process, said first common etch process being designed to have a first etch rate at said via opening and having a second reduced etch rate at said delineation area;
discontinuing said first common etch process when said via opening reaches an etch stop layer located below said dielectric layer; and
forming a trench in an upper portion of said dielectric layer that connects to said via opening and further deepening said delineation area so as to extend to said etch stop layer in a second common etch process.
2. The method of claim 1 , further comprising etching through said etch stop layer in said via opening and said delineation area in a third common etch process.
3. The method of claim 1 , wherein forming said via opening and said delineation area comprises:
forming an anti-reflective coating above said dielectric layer;
forming a resist mask above said anti-reflective coating; and
etching said anti-reflective coating and said dielectric layer with said resist mask acting as an etch mask.
4. The method of claim 1 , wherein forming said via opening and said delineation area comprises:
forming a hard mask layer above said dielectric layer;
forming a resist mask above said hard mask layer;
etching said hard mask layer with said resist mask acting as a first etch mask to form a hard mask;
removing said resist mask; and
etching said dielectric layer with said hard mask acting as a second etch mask.
5. The method of claim 1 , wherein forming said trench comprises:
depositing a fill material to form a fill layer above said via opening and said delineation area; and
patterning said fill material by a means of a resist mask representing said trench.
6. The method of claim 5 , wherein patterning said fill layer comprises removing fill material from said delineation area while preserving a plug of said fill material in said via opening, said plug acting as an etch mask.
7. The method of claim 6 , wherein said fill material comprises a photoresist.
8. The method of claim 7 , wherein removing fill material comprises forming a resist layer above said fill layer, exposing said resist layer and dry-developing said exposed resist layer and said fill layer.
9. The method of claim 8 , wherein dry-developing said exposed resist layer comprises controlling at least one process parameter so as to obtain a reduced removal rate at said delineation area relative to said via opening.
10. The method of claim 8 , wherein dry-developing said resist layer and said fill layer comprises determining an end point of said dry-develop process that defines a substantially exposed state of a bottom of said delineation area as formed after said first common etch process.
11. The method of claim 1 , wherein said dielectric layer comprises a low-k material.
12. The method of claim 1 , wherein said delineation area comprises a trench defining a boundary for a die region.
13. The method of claim 1 , further comprising forming an etch indicator layer in said dielectric layer and controlling said first common etch process on the basis of said etch indicator layer.
14. The method of claim 13 , wherein said etch indicator layer is positioned at a depth that substantially corresponds to a depth of said trench.
15. A method, comprising:
establishing an etch recipe for a first common etch process for forming a via opening and at least one of a delineation trench and an open area in an interlayer dielectric of a metallization layer of a specified type of semiconductor device, said first common etch process being designed to have a first etch rate at said via opening and having a second reduced etch rate at said at least one of a delineation trench and an open area;
forming on one or more substrates said via opening and said at least one of a delineation trench and an open area on the basis of said established process recipe;
discontinuing said first common etch process when said via opening reaches an etch stop layer located below said dielectric layer; and
forming a trench in an upper portion of said dielectric layer that connects to said via opening and further deepening said at least one of a delineation trench and an open area so as to extend to said etch stop layer in a second common etch process.
16. The method of claim 15 , further comprising etching through said etch stop layer in said via opening and said at least one of a delineation trench and an open area in a third common etch process.
17. The method of claim 15 , wherein forming said via opening and said at least one of a delineation trench and an open area comprises:
forming an anti-reflective coating above said dielectric layer;
forming a resist mask above said anti-reflective coating; and
etching said anti-reflective coating and said dielectric layer with said resist mask acting as an etch mask.
18. The method of claim 15 wherein forming said via opening and said at least one of a delineation trench and an open area comprises:
forming a hard mask layer above said dielectric layer;
forming a resist mask above said hard mask layer;
etching said hard mask layer with said resist mask acting as a first etch mask to form a hard mask;
removing said resist mask; and
etching said dielectric layer with said hard mask acting as a second etch mask.
19. The method of claim 15 wherein forming said trench comprises:
depositing a fill material to form a fill layer above said via opening and said at least one of a delineation trench and an open area; and
patterning said fill material by a means of a resist mask representing said trench.
20. The method of claim 19 , wherein patterning said fill layer comprises removing fill material from said at least one of a delineation trench and an open area while preserving a plug of said fill material in said via opening, said plug acting as an etch mask.
21. The method of claim 20 , wherein said fill material comprises a photoresist.
22. The method of claim 21 , wherein removing fill material comprises forming a resist layer above said fill layer, exposing said resist layer and dry-developing said exposed resist layer and said fill layer.
23. The method of claim 22 , wherein dry-developing said exposed resist layer comprises controlling at least one process parameter so as to obtain a reduced removal rate at said delineation trench relative to said via opening.
24. The method of claim 22 , wherein dry-developing said resist layer and said fill layer comprises determining an end point of said dry-develop process that defines a substantially exposed state of a bottom of said at least one of a delineation trench and an open area as formed after said first common etch process.
25. The method of claim 15 , wherein said dielectric layer comprises a low-k material.
26. The method of claim 15 , further comprising forming an etch indicator layer in said dielectric layer and controlling said first common etch process on the basis of said etch indicator layer.
27. The method of claim 26 , wherein said etch indicator layer is positioned at a depth that substantially corresponds to a depth of said trench.
28. The method of claim 1 , further comprising providing at least one precursor gas during said first common etch process to generate an etch inhibitor layer, said etch inhibitor layer reducing the second reduced etch rate relative to the first etch rate.
29. The method of claim 1 , further comprising providing at least one precursor gas during said first common etch process to generate an etch inhibitor layer, said etch inhibitor layer reducing the second reduced etch rate relative to the first etch rate.