Chip bond layout for chip carrier for flip chip applications
View Patent ↗A chip carrier for flip chip applications, according to the present invention, provides peripheral bumps and inner bumps. The inputs and outputs related to the inner bumps are routed out on an additional wiring layer by means of vias. The proposed bond layout provides a high I/O count for a predefined chip size and a predefined carrier technology.
1. A chip carrier for flip chip bond application, comprising:
a first wiring layer;
a second wiring layer;
a plurality of bumps disposed on said first wiring layer;
a first portion of said plurality of bumps representing peripheral bumps and being routed out by said first wiring layer, said peripheral bumps defining a contiguous peripheral bump region;
a second portion of said plurality of bumps representing inner bumps defining an inner bump region and being routed out by said first and second wiring layers; and
at least one via for each inner bump, at least a first portion of said vias being disposed in a first via region, wherein said peripheral bump region surrounds said first via region and said inner bump region and said first via region is disposed between said peripheral bump region and an outer bump region.
2. The chip carrier of claim 1 , further comprising said inner bump region, said peripheral bump region and said via region being arranged in a chip mounting region.
3. The chip carrier of claim 1 , wherein said plurality of bumps disposed on said first wiring layer comprises only peripheral bumps and inner bumps.
4. The chip carrier of claim 1 , wherein said peripheral bumps are arranged in a single row in said peripheral bump region, wherein each peripheral bump is adjacent to two peripheral bumps.
5. The chip carrier of claim 1 , wherein said inner bump region comprises an inner region, an intermediate region and an outer region.
6. The chip carrier of claim 5 , wherein at least one of said inner region, said intermediate region and said outer region is a concentrically arranged region.
7. The chip carrier of claim 5 , wherein said outer region is disposed adjacent to said peripheral bump region.
8. The chip carrier of claim 5 , wherein at least a second portion of said vias is disposed in a second via region defined by said inner region and said intermediate region.
9. The chip carrier of claim 8 , wherein said first via region comprises an intermediate via region adjacent to said intermediate region and a peripheral via region adjacent to said peripheral bump region.
10. The chip carrier of claim 8 , wherein each inner bump of said inner region is connected to a first via disposed in said inner via region.
11. The chip carrier of claim 10 , wherein each first via disposed in said inner via region is further connected to a second via disposed in said inner via region.
12. The chip carrier of claim 11 , wherein the diameter of said second via is greater than the diameter of said first via.
13. The chip carrier of claim 9 , wherein each inner bump of said intermediate region is connected to a first via disposed in said intermediate via region.
14. The chip carrier of claim 9 , wherein each inner bump of said outer region is connected to a first via disposed in said peripheral via region.
15. The chip carrier of claim 9 , wherein the bumps and the first and second via are arranged to provide for a predetermined carrier technology the maximum number of electrically connected bumps.
16. The chip carrier of claim 1 , wherein the chip carrier material comprises FR4.
17. The chip carrier of claim 1 , further comprising a power supply layer.
18. The chip carrier of claim 17 , wherein conductive lines from the inner bumps of the inner region are routed out by the power supply layer.
19. The chip carrier of claim 1 , further comprising a solder mask.
20. The chip carrier of claim 19 , wherein said solder mask comprises at least one block solder mask to block the flow of the solder material of a plurality of bumps.
21. The chip carrier of claim 20 , wherein said at least one block solder mask is concentrically arranged on the chip mounting region.