Technique for forming a strained transistor by a late amorphization and disposable spacers
View Patent ↗By using a disposable spacer approach for forming drain and source regions prior to an amorphization process for re-crystallizing a semiconductor region in the presence of a stressed spacer layer, possibly in combination with enhanced anneal techniques, such as laser and flash anneal processes, a more efficient strain-generating mechanism may be provided. Furthermore, the spacer for forming the metal silicide may be provided with reduced width, thereby positioning the respective metal silicide regions more closely to the channel region. Consequently, an overall enhanced performance may be obtained on the basis of the above-described techniques.
1. A method, comprising:
forming a first doped region in a substantially crystalline semiconductor layer adjacent to a gate electrode having formed on sidewalls thereof a first sidewall spacer structure;
removing said first sidewall spacer structure;
forming a substantially amorphized region in said semiconductor layer and said first doped region;
forming a stressed layer having a specified intrinsic stress at least above a portion of said semiconductor layer; and
re-crystallizing said substantially amorphized region in the presence of said stressed layer by performing a heat treatment.
2. The method of claim 1 , wherein forming said first doped region comprises performing at least one ion implantation process and annealing said semiconductor layer prior to removing said first sidewall spacer structure.
3. The method of claim 1 , wherein forming said first doped region comprises performing at least one ion implantation process and annealing said semiconductor layer after removing said first sidewall spacer structure.
4. The method of claim 1 , wherein forming said first doped region comprises forming a first spacer of said first sidewall spacer structure and performing a first implantation process, forming a second spacer adjacent to said first spacer and performing a second ion implantation process.
5. The method of claim 4 , wherein said first and second spacers are formed in direct contact with each other.
6. The method of claim 1 , further comprising forming a second doped region after removing said first sidewall spacer structure and prior to re-crystallizing said substantially amorphized region.
7. The method of claim 6 , further comprising annealing said semiconductor layer to activate at least dopants in said second doped region prior to re-crystallizing said substantially amorphized region.
8. The method of claim 7 , wherein annealing said semiconductor layer is performed by at least one of a laser anneal process and a flash anneal process.
9. The method of claim 1 , further comprising forming a second sidewall spacer structure from said stressed layer, said second sidewall spacer structure having a reduced width compared to said first sidewall spacer structure.
10. The method of claim 9 , further comprising forming a metal silicide at least in said second doped region on the basis of said second sidewall spacer structure.
11. The method of claim 10 , further comprising forming a stressed layer above said gate electrode and said first and second doped regions to create strain in a channel region formed adjacent to said second doped region.
12. A method, comprising:
forming a first P-doped region adjacent to a first gate electrode and a first N-doped region adjacent to a second gate electrode, said first and second gate electrodes located above a semiconductor layer and having formed on sidewalls thereof a first spacer structure;
substantially amorphizing at least a portion of said semiconductor layer;
removing said first spacer structure from said first and second gate electrodes;
forming a stressed layer having a first type of intrinsic stress above at least a portion of said first P-doped region;
forming a stressed layer having a second type of intrinsic stress above at least a portion of said first N-doped region, said first type of intrinsic stress differing from said second type; and
heat treating said semiconductor layer to substantially re-crystallize said substantially amorphized portion.
13. The method of claim 12 , wherein said substantially amorphized portion is substantially amorphized after removing said first spacer structure.
14. The method of claim 13 , further comprising annealing said first P-doped and N-doped regions prior to removing said first spacer structure.
15. The method of claim 14 , wherein annealing said first P-doped region and said first N-doped region comprises performing at least one of a laser anneal process and a flash anneal process.
16. The method of claim 11 , further comprising forming a second P-doped region and a second N-doped region adjacent to said first P-doped and N-doped regions, respectively, after removing said first spacer structure.
17. The method of claim 16 , further comprising annealing said second P-doped and N-doped regions prior to substantially re-crystallizing said substantially amorphized portion.
18. The method of claim 17 , wherein annealing said second P-doped region and said second N-doped region comprises performing at least one of a laser anneal process and a flash anneal process.
19. The method of claim 12 , wherein said first type of intrinsic stress is compressive stress and said second type of intrinsic stress is a tensile stress.